Signal transfer across a voltage domain boundary
First Claim
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1. A processor comprising:
- a first voltage domain;
a second voltage domain;
a first level shifter configured to transfer a reset signal from the first voltage domain to the second voltage domain;
a second level shifter configured to transfer a clock signal from the first voltage domain to the second voltage domain; and
a third level shifter configured to transfer a data signal from the first voltage domain to the second voltage domain, wherein the data signal comprises a start bit, an address bit, and a data bit.
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Abstract
A circuit and method are provided enabling the transfer of signals from a first voltage domain to a second voltage domain. The circuit comprises level shifters enabling the signal transfer, and is space-efficient and power efficient. A 3-wire serial protocol is used to enable the serial transmission of signals across the voltage domain boundary, and provides two distinct reset states.
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Citations
17 Claims
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1. A processor comprising:
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a first voltage domain; a second voltage domain; a first level shifter configured to transfer a reset signal from the first voltage domain to the second voltage domain; a second level shifter configured to transfer a clock signal from the first voltage domain to the second voltage domain; and a third level shifter configured to transfer a data signal from the first voltage domain to the second voltage domain, wherein the data signal comprises a start bit, an address bit, and a data bit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of transferring signals from a first voltage domain of a processor to a second voltage domain of a processor, the method comprising acts of:
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using a first level shifter to transfer a reset signal from the first voltage domain to the second voltage domain; using a second level shifter to transfer a clock signal from the first voltage domain to the second voltage domain; and using a third level shifter to transfer a data signal from the first voltage domain to the second voltage domain; wherein data is transferred from the first voltage domain to the second voltage domain in response to the reset signal being in a low state and the clock signal being in a high state. - View Dependent Claims (15, 16, 17)
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Specification