Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals

• US 7,093,145 B2
• Filed: 07/30/2004
• Issued: 08/15/2006
• Est. Priority Date: 10/19/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Sidiropoulos, Stefanos, Horowitz, Mark, Best, Scott, Chau, Pak, Werner, Carl
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): SURYAWANSHI, SURESH
• Application Number:
  US10/903,572
• Publication Number:
  US 20050005179A1
• Time in Patent Office: 746 Days
• Field of Search: 713/300, 714/718, 710/110, 327/108, 702/64
• US Class Current: 713/300
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0296 Arrangements to ensure DC-balance
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 : Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4902 : Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 7/0331 : with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.

Claims

1. A current controller, comprising:

a voltage generator that generates a reference voltage signal, wherein a potential of the reference voltage signal is selected from a plurality of reference voltage levels;

a node to supply a selected source calibration signal, wherein the selected source calibration signal is selected from a plurality of source calibration signals;

a comparator coupled with the voltage generator and the node, wherein the reference voltage signal and the selected source calibration signal are applied to the comparator; and

a source calibration signal adjustment circuit to adjust the selected source calibration signal in accordance with an output signal of the comparator.

2. A current controller as claimed in claim 1, wherein the selected calibration signal comprises a voltage associated with a predetermined data symbol.

3. A current controller as claimed in claim 2, wherein the predetermined data symbol represents two data bits.

4. A current controller as claimed in claim 3, wherein the voltage generator produces at least three reference voltage levels.

5. A current controller as claimed in claim 2, wherein the predetermined data symbol represents more than two data bits.

6. A current controller as claimed in claim 5, wherein the voltage generator produces at least three reference voltage levels.

7. A current controller as claimed in claim 1, wherein the source calibration signal adjustment circuit comprises a plurality of semiconductor switches.

8. A current controller as claimed in claim 1, wherein the reference voltage signal and the selected source calibration signal are applied to the comparator via a multiplexer.

9. A current controller as claimed in claim 1, wherein the selected source calibration signal comprises a first signal and a second signal, wherein the first signal is associated with a known voltage level and the second signal is associated with an unknown voltage level.

10. A current controller as claimed in claim 1, wherein the reference voltage generator generates the plurality of reference voltage levels based on at least one externally supplied voltage.