Wavefront clock synchronization
First Claim
1. An arrangement of integrated circuit cells comprising:
- at least one cell comprising a root clock source generating a root clock signal;
at least one other cell having at least one clock domain, said at least one clock domain having a clock source generating a time-delayed clock signal which is a time-delayed version of the root clock signal, wherein the time delayed clock signal is delayed with respect to the root clock signal by a time corresponding to a data propagation delay for data to propagate from the root clock source to the clock source of the clock domain;
at least one data line; and
at least one delay element,wherein said integrated circuit cells are arranged in a row including a first cell situated at a first end of said row, wherein the at least one cell is said first cell, and wherein the at least one clock domain is associated with the root clock of the first cell, the row further comprising a second cell having a clock source and being situated at a second end of the row, wherein the at least one data line, and the at least one delay element electrically couple the first cell to the second cell, and are adapted to cause a time-delay to the electrical signals travelling therethrough to bring data signals in phase with the clock source of the second cell into phase at the first cell with the root clock source.
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Abstract
The invention provides for the arrangement and management of timing of various domains on a large integrated circuit which introduces a phase offset between clock domains of neighboring cells to create a wavefront clock which propagates through the circuit at the same speed data propagates though the circuit. The cells of the integrated circuit are wavefront clock synchronized in that the phase offset introduced in a particular cell'"'"'s clock is such that the arrival of a skewed clock and propagation delayed data from that cell'"'"'s neighbor is synchronized with that particular cell'"'"'s own clock. Wavefront clock synchronization mitigates at least some of the problems of clock skew and the associated effects of slowing data propagation and reduction of clock frequencies associated with large surface integrated circuits utilizing synchronized clock domains.
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Citations
8 Claims
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1. An arrangement of integrated circuit cells comprising:
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at least one cell comprising a root clock source generating a root clock signal; at least one other cell having at least one clock domain, said at least one clock domain having a clock source generating a time-delayed clock signal which is a time-delayed version of the root clock signal, wherein the time delayed clock signal is delayed with respect to the root clock signal by a time corresponding to a data propagation delay for data to propagate from the root clock source to the clock source of the clock domain; at least one data line; and at least one delay element, wherein said integrated circuit cells are arranged in a row including a first cell situated at a first end of said row, wherein the at least one cell is said first cell, and wherein the at least one clock domain is associated with the root clock of the first cell, the row further comprising a second cell having a clock source and being situated at a second end of the row, wherein the at least one data line, and the at least one delay element electrically couple the first cell to the second cell, and are adapted to cause a time-delay to the electrical signals travelling therethrough to bring data signals in phase with the clock source of the second cell into phase at the first cell with the root clock source. - View Dependent Claims (2, 3, 4)
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- 5. A cell of an integrated circuit having a first clock domain and a second clock domain, said first clock domain and said clock domain each having a clock source, said cell having at least one neighboring cell and adapted to accept data in a first direction of propagation and a second direction of propagation opposite to the direction of the first direction of propagation, wherein the at least one neighboring cell comprises a first neighboring cell and a second neighboring cell, said first and second neighboring cell each having a neighboring cell clock source generating a neighboring cell clock signal, wherein said clock source generates a time-delayed clock signal which is a time-delayed version of the neighboring cell clock signal of the respective neighboring cell, wherein the time-delayed clock signal is delayed with respect to the neighboring cell clock signal by a time corresponding to a data propagation delay for data to propagate from the neighboring cell clock source to the clock source of said cell.
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8. A cell of an integrated circuit, comprising a plurality of clock domains for clocking signals in at least two directions of propagation, the cell being disposed between a first neighbor cell and a second neighbor cell, the first neighbor cell situated adjacent said cell along a first one of the at least two directions of propagation and having a first neighbor clock source generating a first neighbor clock signal, the second neighbor cell situated adjacent said cell along a second one of the at least two directions of propagation and having a second neighbor clock source generating a second neighbor clock signal, wherein said plurality of clock domains includes a first clock domain and a second clock domain, wherein said first clock domain includes a first clock source generating a first time-delayed clock signal that is delayed with respect to the first neighbor clock signal by a time required for data to propagate from the first neighbor clock source to the first clock source of said cell, wherein said second clock domain includes a second clock source generating a second time-delayed clock signal that is delayed with respect to the second neighbor clock signal by a time required for data to propagate from the second neighbor clock source to the second clock source of said cell.
Specification