Semiconductor device and an electronic device

• US 7,095,117 B2
• Filed: 09/14/2004
• Issued: 08/22/2006
• Est. Priority Date: 10/18/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Atsushi Nakamura, Hideshi Fukumoto, Motoo Suwa, Yuichi Mabuchi
• Inventors: Suwa, Motoo, Nakamura, Atsushi, Mabuchi, Yuichi, Fukumoto, Hideshi
• Primary Examiner(s): Tran, Mai-Huong
• Application Number:
  US10/939,491
• Publication Number:
  US 20050029648A1
• Time in Patent Office: 707 Days
• Field of Search: 257/691, 257/698, 257/700, 257/778, 257/780
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A semiconductor device has a reduced number of external power terminals and is scaled down while suppressing power noise, and an electronic device is efficiently equipped with a bypass condenser. A package substrate has, on its surface, a semiconductor chip having a plurality of output circuits and at least one electrode for supplying a voltage to each of the output circuits, and is provided with external terminals on its back surface and has a plurality of wiring layers.

Claims

1. A semiconductor device comprising:

a package substrate having a multilayer structure;

a semiconductor chip mounted on a main surface of said package substrate;

wherein said semiconductor chip includes,

an internal circuit;

an I/O circuit interacting a signal between said internal circuit and an external device;

a first voltage supply electrode which supplies a first operating voltage to said internal circuit; and

a second voltage supply electrode which supplies a second operating voltage, being different from said first operating voltage, to said I/O circuit, and

wherein said package substrate includes,

a first electrode provided on said main surface of said package substrate and being electrically coupled to said first voltage supply electrode of said semiconductor chip;

a second electrode provided on said main surface of said package substrate and being electrically coupled to said second voltage supply electrode of semiconductor chip;

a first wiring plane being formed of a wiring layer which is different from said first and second electrodes and being electrically coupled to said first electrode via a through hole;

a second wiring plane being formed of the same wiring layer as that of said first wiring plane and being electrically coupled to said second electrode via a through hole;

a third wiring plane being formed of a wiring layer which is different from both said first and second wiring planes and each of said first and second electrodes, said third wiring plane commonly supplying a reference potential to said internal circuit and said I/O circuit of said semiconductor chip;

third electrodes provided on said back surface opposing to said main surface of said package substrate; and

said third electrodes being used as external terminals of said package substrate,

wherein said first wiring plane and said second wiring plane are separated from each other in a plane view.

2. The semiconductor device according to claim 1,

wherein said semiconductor chip includes a plurality of I/O circuits each of which outputs a signal formed by said internal circuits,

said plurality of second voltage supply electrodes which supplies different operating voltages each other to said plurality of I/O circuits.

3. The semiconductor device according to claim 1, wherein said second wiring plane having a plurality of wiring layers which are separated from each other in a plane view.

4. The semiconductor device according to claim 1, wherein said package substrate is provided with a plurality of external terminals which connected via a fourth wiring plane being formed of a wiring layer which is different from said first, second and third wiring plane and each of said first and second electrodes.

5. The semiconductor device according to claim 1,

wherein the number aggregated to the number less than said second electrodes is 4 or more, and

wherein these 4 or more external terminals are dispersively laid out in areas obtained by dividing an area formed with external terminals on the back surface into quarters.

6. The semiconductor device according to claim 5, wherein said first wiring plane which commonly coupled said second electrodes respectively, is electrically isolated and divided into two or more sets and makes it possible to supply different operating voltages from external terminals to their corresponding sets.

7. The semiconductor device according to claim 6, wherein said semiconductor chip and the corresponding electrodes on said package substrate are coupled to one another in a flip-flop configuration.

8. The semiconductor device according to claim 6, wherein said semiconductor chip and the corresponding electrodes on said package substrate are coupled to one another in a wire-bonding configuration.

9. The semiconductor device according to claim 1,

wherein external terminals for supplying operating voltages to said internal circuit are provided inside a back surface corresponding to a position where said semiconductor chip is mounted, and

wherein external terminals for supplying operating voltages to said I/O circuits and external terminals for the input or output of signals are provided outside the back surface corresponding to the position where said semiconductor chip is mounted.

10. A semiconductor device comprising:

a package substrate having a multilayer structure;

a semiconductor chip mounted on a main surface of said package substrate;

wherein said semiconductor chip includes,

an internal circuit;

an I/O circuit interfacing a signal between said internal circuit and an external device;

a first voltage supply electrode which supplies a first operating voltage to said internal circuit; and

a second voltage supply electrode which supplies a second operating voltage, being different from said first operating voltage, to said I/O circuit, and

wherein said package substrate includes,

a first electrode provided on said main surface of said package substrate and being electrically coupled to said first voltage supply electrode of said semiconductor chip;

a second electrode provided on said main surface of said package substrate and being electrically coupled to said second voltage supply electrode of semiconductor chip;

a first wiring plane being formed of a wiring layer which is different from said first and second electrodes and being electrically coupled to said first electrode via a through hole;

a second wiring plane being formed of the same wiring layer as that of the said first wiring plane and being formed outside said first wiring plane and being electrically coupled to said second electrode via a through hole;

a third wiring plane being formed of a wiring layer which is different from both said first and second wiring planes and each of said first and second electrodes, said third wiring plane commonly supplying a reference potential to said internal circuit and said I/O circuit of said semiconductor chip;

third electrodes provided on said back surface opposing to said main surface of said package substrate; and

said third electrodes being used as external terminals of said package substrate,

wherein said first wiring plane and said second wiring plane are separated from each other in a plane view.

11. The semiconductor device according to claim 10,

wherein said semiconductor chip includes a plurality of I/O circuits each of which outputs a signal formed by said internal circuit,

said plurality of second voltage supply electrodes which supplies different operating voltages each other to said plurality of I/O circuits.

12. The semiconductor device according to claim 10, wherein said second wiring plane having a plurality of wiring layers which are separated from each other in a plane view.

13. The semiconductor device according to claim 10, wherein said package substrate is provided with a plurality of external terminals which connected via a fourth wiring plane being formed of a wiring layer which is different from said first, second and third wiring plane and each of said first and second electrodes.

14. The semiconductor device according to claim 10, wherein the number aggregated to the number less than said second electrodes is 4 or more, and

wherein these 4 or more external terminals are dispersively laid out in areas dividing an area formed with external terminals on the back surface into quarters.

15. The semiconductor device according to claim 14, wherein said first wiring plane which commonly coupled said second electrodes respectively, is electrically isolated and divided into two or more sets and makes it possible to supply different operating voltages from external terminals to their corresponding sets.

16. A semiconductor device comprising:

a package substrate having a plane formed in a quadrangle shape and a multilayer structure;

a semiconductor chip mounted on a main surface of said package substrate;

wherein said semiconductor chip includes,

an internal circuit;

an I/O circuit interfacing a signal between said internal circuit and an external device;

a first voltage supply electrode which supplies a first operating voltage to said internal circuit; and

a second voltage supply electrode which supplies a second operating voltage, being different from said first operating voltage, to said I/O circuit, and

wherein said package substrate includes,

a first electrode provided on said main surface of said package substrate and being electrically coupled to said first voltage supply electrode of said semiconductor chip;

a second electrode provided on said main surface of said package substrate and being electrically coupled to said second voltage supply electrode of semiconductor chip;

a first wiring plane being formed of a wiring layer which is different from said first and second electrodes and being electrically coupled to said first electrode via a through hole;

a second wiring plane being formed of the same wiring layer as that of said first wiring plane and being electrically coupled to said second electrode via a through hole;

a third wiring plane being formed of a wiring layer which is different from both said first and second wiring plane and each of said first and second electrodes, said third wiring plane commonly supplying a reference potential to said internal circuit and said I/O circuit of said semiconductor chip;

third electrodes provided on said back surface opposing to said main surface of said package substrate; and

said third electrodes being used as external terminals of said package substrate,

wherein said external terminals and said second wiring plane are provided between one side of said package substrate and said first wiring plane,

wherein said external terminals are provided between said one side of said package substrate and said second wiring plane,

wherein said first wiring plane and said second wiring plane are separated from each other in a plane view.

17. The semiconductor device according to claim 16,

wherein said external terminals and said second wiring plane are provided between opposite side opposing to said one side of said package substrate and said first wiring plane,

wherein said external terminals are provided between said opposite side and said second wiring plane.

18. The semiconductor device according to claim 16, wherein said package substrate is provided with a plurality of external terminals which connected via a fourth wiring plane being formed of a wiring layer which is different from said first, second and third wiring plane and each of said first and second electrodes.

19. The semiconductor device according to claim 16, wherein the number aggregated to the number less than said second electrodes is 4 or more, and

wherein these 4 or more external terminals are dispersively laid out in areas obtained by dividing an area formed with external terminals on the back surface into quarters.

20. The semiconductor device according to claim 19, wherein said first wiring plane which commonly coupled said second electrodes respectively, is electrically isolated and divided into two or more sets and makes it possible to supply different operating voltages from external terminals to their corresponding sets.