Clock gating for synchronous circuits

• US 7,095,251 B2
• Filed: 01/20/2004
• Issued: 08/22/2006
• Est. Priority Date: 01/20/2003
• Status: Expired due to Fees

• Current Assignee: Azuro UK Ltd (Cadence Group)
• Original Assignee: Azuro UK Ltd (Cadence Group)
• Inventors: Cunningham, Paul Alexander, Wilcox, Stephen Paul
• Primary Examiner(s): Le, Don P.
• Application Number:
  US10/760,900
• Publication Number:
  US 20040150427A1
• Time in Patent Office: 945 Days
• Field of Search: 326 93- 98
• US Class Current: 326/93
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

There is disclosed a clock gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, the clocked gating structure including at least one full-cycle clock gating cell and at least one half-cycle clock gating cell, and a method for designing and controlling such.

Claims

1. A clock gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, with at least one clocked state holding element being a full-cycle clock gating cell and at least one further clocked state holding element being a half-cycle clock gating cell.

2. The clock gating structure according to claim 1 wherein the at least one full-cycle and at least one half-cycle clock gating cells are associated with a same clock source.

3. The clock gating structure according to claim 1 wherein said clock gating structure is a hierarchical clock structure wherein the output of at least one clock gating cell forms a clock input to at least one further clock gating cell.

4. The clock gating structure according to claim 1 wherein the output of at least one clock gating cell is shared by a plurality of clocked state holding elements.

5. The clock gating structure according to claim 3 in which the at least one clock gating cell is a half-cycle clock gating cell and the at least one further clock gating cell is a full-cycle clock gating cell.

6. A method of forming a gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, said method comprising the step of selecting, for each clocked state holding element or group of clocked state holding elements, a gating cell from a group consisting of a full-cycle clock gating cell and a half-cycle clock gating cell, wherein at least one gating cell in said gating structure is chosen to be a full-cycle clock gating cell and at least one other gating cell in said gating structure is chosen to be a half-cycle clock gating cell.

7. The method according to claim 6 wherein said selecting step is dependent on timing criteria for each clocked state holding element.

8. The method according to claim 7 wherein if a half-cycle clock gate meets the timing criteria for a clocked state holding element or group of clocked state holding elements, the half-cycle clock gate is selected.

9. The method according to claim 6 further comprising the steps of:

generating at least one gating expression for each element;

determining any common gating expressions; and

for each common gating expression, providing a single shared clock gate for the associated elements.

10. The method according to claim 9 wherein there is provided a hierarchical clock gating structure, the method further comprising the steps of:

determining the number of elements sharing a common expression; and

allocating those expressions having a higher number of shared elements to a clock gate at a higher level of the hierarchical structure.

11. The method according to claim 9 further comprising the step of minimizing each gating expression.

12. The method according to claim 11 wherein the minimizing step further comprises the step of applying a maximal conjunctive form technique to each gating expression.

13. The method according to claim 10, wherein the hierarchical gating structure comprises a plurality of half-cycle gates and full-cycle gates.

14. The method according to claim 13 wherein the method comprises associating full and half-cycle gates with a same clock source.

15. The method according to claim 14 wherein the full and half cycle clock gating cells are arranged in sequence in the hierarchy, wherein the half-cycle clock gating cell is above the full-cycle clock gating cell.

16. The method of claim 6 wherein the step of selecting is performed by a computer code stored in a computer readable medium.

17. A computer readable medium for enabling a computer to design a gating structure comprising a computer program code for performing the method for forming a gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, said method comprising selecting either a full-cycle clock gating cell or a half-cycle clock gating cell for each clocked state holding element or group of clocked state holding elements;

wherein at least one gating cell in said gating structure is chosen in be a full-cycle clock gating cell and at least one other gating cell in said gating structure is chosen to be a half-cycle clock gating cell; and

wherein the computer program code is executed by the computer.

18. An apparatus for forming a gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, and means for selecting either a full-cycle clock gating cell or a half-cycle clock gating cell for each clocked state holding element or group of clocked state holding elements;

wherein at least one gating cell in said gating structure is chosen to be a full-cycle clock gating cell and at least one other gating cell in said gating structure is chosen to be a half-cycle clock gating cell.

19. The apparatus according to claim 18 wherein said selecting means is controlled by timing criteria for each clocked state holding element.

20. The apparatus according to claim 19 wherein if a half-cycle clock gate meets the timing criteria for a clocked state holding element or group of clocked state holding elements, the half-cycle clock gate is selected.

21. The apparatus according to claim 18 further comprising:

means for generating at least one gating expression for each element;

means for determining any common gating expressions; and

means for providing, for each common gating expression, a single shared clock gate for the associated elements.

22. The apparatus according to claim 21 wherein there is provided a hierarchical clock gating structure, the apparatus further comprising means for determining the number of elements sharing a common expression;

and means for allocating those expressions having a higher number of shared elements to a clock gate at a higher level of the hierarchical structure.

23. The apparatus according to claim 21 further comprising means for minimizing each gating expression.

24. The apparatus according to claim 22 further comprising means for associating full and half-cycle gates with a same clock source.

25. The apparatus according to claim 24 further comprising means for providing full and half cycle clock gating cells in sequence in the hierarchy, wherein the half-cycle clock gating cell is above the full-cycle clock gating cell.

26. A computer system including an apparatus for forming a gating structure for a synchronous circuit, said apparatus comprising a plurality of clocked state holding elements, and means for selecting either a full-cycle clock gating cell or a half-cycle clock gating cell for each clocked state holding element or group of clocked state holding elements.