Circuit and method for lowering insertion loss and increasing bandwidth in MOSFET switches

• US 7,095,266 B2
• Filed: 08/18/2004
• Issued: 08/22/2006
• Est. Priority Date: 08/18/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Miske, Myron J.
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US10/920,882
• Publication Number:
  US 20060038604A1
• Time in Patent Office: 734 Days
• Field of Search: 327/389, 327/427, 327/431, 327/434, 327534-535, 327/537, 327/543, 327/546, 327/437, 327/404, 327/379
• US Class Current: 327/427
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A DC symmetrical FET switch includes second and third switches connecting the well of the symmetrical FET switch to the drains and the source when the symmetrical FET switch is on. When the three FET'"'"'s are on, the well, source and drain of the symmetric FET switch all exhibit the same input signal, wherein the drains and source to well capacitances are substantially prevented from draining off any of the input signal, thereby increasing the bandwidth and decreasing the insertion loss of the switch. The second and third switches are also FET switches. An enable signal is connected to the gates of all three FET'"'"'s turning them on and off together. When the enable is false the FET switches are turned off and their wells are driven to a potential a proper potential. When the FET'"'"'s are n-type the potential is low and when the FET'"'"'s are p-types the potential is high. A resistor is provided in the gate drive of the first FET switch that further increases bandwidth and decreases insertion loss of the switch by moving the break frequency of the drain and source to gate capacitances.

Claims

1. A symmetric DC switch comprising:

a first field effect transistor (FET) having gate, source, drain and well contacts, wherein the source or the drain contact receives an input signal, an output signal substantially equal to the input signal is presented to the respective drain or source contact when the FET is on,

a second FET arranged, when on, to connect the source to the well of the first FET,

a third FET arranged, when on, to connect the drain to the well of the first FET, wherein the first second and third FET'"'"'s are all on and off together, wherein the input signal appears at the source, drain and well of the first FET when the FET'"'"'s are on, and

a switch arranged between the well of the first FET and a potential, wherein the well is connected to the potential when the first FET is off, and

a resistor arranged between an enable signal and the gate of the first FET, the enable signal, when true, turning on the first, second and third FET'"'"'s and, when false, turning them off, wherein the bandwidth of the first FET, when on, is increased and the insertion loss reduced.

2. The switch of claim 1 further comprising switching circuitry connected directly to the gate of the first FET, wherein when the enable signal is false, the switching circuitry drives the gate directly, bypassing the resistor, providing faster turn off of the first FET.

3. The switch of claim 2, wherein the switching circuitry comprises fourth FET switch having a gate that received the enable signal, the fourth FET having a source and drain connected to provide a path between the gate of the first FET and a first potential that turns off the first FET, when the fourth FET is on.

4. The switch of claim 3 further comprising a fifth FET arranged to receive the enable signal at its gate, the fifth FET having a source and drain connected to provide a path between the resistor and a second potential that turns on the first FET when the enable is true.

5. A symmetric DC coupled switch comprising:

a first FET having an input for receiving a signal and an output wherein the signal is provided when the switch is on, the first FET having a gate and a well,

a second FET arranged when on for connecting the well to the input,

a third FET arranged when on for connecting the well to the output, wherein the gates of the first, second and third FET'"'"'s all receive an enable signal and are all on when the enable is true and are all off when the enable is false, and

a fourth FET arranged when on for connecting the well of the first FET to a potential, the fourth FET is turned on by the enable being false, and

a resistor arranged between an enable signal and the gate of the first FET, the enable signal, when true, turning on the first, second and third FET'"'"'s and, when false, turning them off, wherein the bandwidth of the first FET, when on, is increased and the insertion loss reduced.

6. The switch of claim 5 wherein the FET'"'"'s are all n-type.

7. The switch of claim 5 wherein the FET'"'"'s are all p-types.

8. The symmetric DC coupled switch of claim 7 further comprising:

a first n-type FET having an input for receiving a signal and an output wherein the signal is provided when the switch is one, the first n-type FET having a gate and a well,

a second n-type FET arranged when on for connecting the well to the input,

a third n-type FET arranged when on for connecting the well to the output, wherein the gates of the first, second and third n-type FET'"'"'s all receive an enable signal and are all on when the enable is true and are all off when the enable is false, and

a fourth n-type FET arranged when on for connecting the well of the first n-type FET to a potential, the fourth n-type FET is turned on by the enable being false.

9. A method for decreasing insertion loss and increasing bandwidth of a symmetric DC switch, the method comprising the steps of:

providing a first FET having an input for receiving a signal, and an output, gate and well;

connecting an enable signal to the gate, wherein the enable when true turns the first FET on,

delivering the signal to the output when the first FET is on,

connecting the well to the input and the well to the output when the first FET is on,

connecting the well to a potential when the first FET is off, and

arranging a resistor between the enable signal and the gate of the first FET, wherein the bandwidth of the first FET, when on, is increased and the insertion loss is reduced.

10. The method of claim 9 further comprising the step of:

connecting switching circuitry between the enable signal and the gate of the first FET, wherein when the enable signal is false, the switching circuitry drives the gate directly, bypassing the resistor, turning off the first FET.

11. The method of claim 10 further comprising the step of connecting the gate of the first FET to a first potential that turns off the first FET when the enable is false.

12. The method of claim 11 further comprising the step of:

providing a path between the resistor and a second potential that turns on the first FET when the enable is true.