A/D converter with minimized transfer error

• US 7,095,346 B2
• Filed: 10/26/2004
• Issued: 08/22/2006
• Est. Priority Date: 11/27/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Bogner, Peter
• Primary Examiner(s): Nguyen, John B
• Application Number:
  US10/973,656
• Publication Number:
  US 20050116846A1
• Time in Patent Office: 665 Days
• Field of Search: 341/155, 341/144, 341/145, 341/156, 341/122, 341/118, 341/120, 341/172
• US Class Current: 341/120
• CPC Class Codes: H03M 1/109 for dc performance, i.e. static testing H03M1/1085 takes precedence
• CPC Class Codes: H03M 1/167 all stages comprising simultaneous converters H03M1/165 takes precedence
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

An A/D converter has at least one converter stage which, respectively, has a sample and hold circuit for sampling an analog input signal. The converter stage also includes a comparator unit that compares the analog input signal with a reference value in order to produce a digital output value from the converter stage, a digital/analog converter for converting the digital output value into an analog signal, a subtractor for subtracting the analog signal from the sampled input signal, a signal amplifier for amplifying the output signal which is output by the subtractor with a particularl singal gain factor for the next converter stage, and a weighting unit for multiplying the digital output value by a multiplier for addition to further weighted output values from converter stages to produce the digital output value from the A/D converter.

Claims

1. An analog to digital converter comprising:

a sample and hold circuit operable to sample an input signal;

a comparator unit operable to compare the input signal to a reference signal, and to provide a digital output value based upon the comparison;

a digital to analog converter (DAC) including a calibration capacitor and a plurality of DAC capacitors, the DAC operably connected to the comparator unit to receive the digital output value, the DAC operable to convert the digital output value into an analog signal;

a subtractor operably connected to receive the sampled input from the sample and hold circuit and the digital output value from the DAC, the subtractor operable to subtract the analog signal from the sampled input signal and to generate a remainder based thereon;

an amplifier operably connected to receive the remainder from the subtractor and operable to output an amplified remainder based upon the remainder;

a weighting unit operable to receive the digital output value from the comparator and operable to provide a weighted digital output value by multiplying the digital output with a received multiplier signal;

a switch device operable to switch a received calibration signal to the calibration capacitor and further to each of the plurality of DAC capacitors; and

a calibration unit operably connected to receive the calibration signal and the output of the amplifier and operable to control the switch device and to calculate the respective signal gains of each of the plurality of DAC capacitors in order to calculate information representative of a transfer error.

2. The analog to digital converter of claim 1, further comprising:

a DAC error subtractor operable to receive the weighted digital output value from the weighting unit and the information representative of a transfer error from the calibration unit, the DAC error subtractor operable to subtract the information representative of a transfer error from the weighted digital output value.

3. The analog to digital converter of claim 1, wherein the calibration unit further comprises:

a register operable to store the calculated signal gains of each of the plurality of DAC capacitors and the calibration capacitor.

4. The analog to digital converter of claim 3, wherein the calibration unit is further operable to calculate a mean value of the stored calculated signal gains of the plurality of DAC capacitors.

5. The analog to digital converter of claim 4, wherein the calibration unit is further operable to output the calculated mean value as the multiplier.

6. The analog to digital converter of claim 1, wherein the calibration unit comprises:

an adjustable calibration amplifier operable to receive the calibration signal and to output the multiplier to the weighting unit and to output an amplified calibration signal, wherein the amplified calibration signal is equal to the calibration signal multiplied by the multiplier, and wherein the multiplier value is established in response to a setting signal;

a subtractor operable to receive the amplified remainder from the amplifier and the amplified calibration signal from the adjustable calibration amplifier, the subtractor operable to subtract the amplified remainder from the amplified calibration signal to output a difference signal; and

an evaluation unit operable to receive the calibration signal and the difference signal, the evaluation unit operable to correlate the difference signal with the calibration signal to generate the setting signal.

7. The analog to digital converter of claim 6, wherein:

the calibration signal is a digital random signal; and

the evaluation unit is operable to cross-correlate the difference signal with the digital random signal to output the setting signal.

8. The analog to digital converter of claim 7, wherein the evaluation unit further comprises a filter operable to receive the setting signal and operable to filter the setting signal in order to output a filtered setting signal to the calibration amplifier.

9. The analog to digital converter of claim 1, wherein the calibration unit comprises:

a flow controller operable to generate control signals to control the switch device.

10. The analog to digital converter of claim 1, wherein the comparator unit is further operable to provide a thermometer coded digital output value.

11. The analog to digital converter of claim 1, wherein the sample and hold circuit, the comparator unit, the DAC, the subtractor, the amplifier, the weighting unit and the switch device are within a first converter stage, the analog to digital converter further comprising:

a second converter stage operable to receive the amplified remainder from the amplifier of the first converter stage.

12. The analog to digital converter of claim 1, wherein the calibration signal is a digital random signal generated by a random signal generator.

13. The analog to digital converter of claim 1, wherein the analog to digital converter is a fully differential analog to digital converter.

14. An analog to digital pipeline converter comprising:

a digital to analog converter (DAC) including a plurality of DAC capacitors and a calibration capacitor, the DAC operable to receive an analog signal; and

a switching device switchably connected to the plurality of DAC capacitors and the calibration capacitor, the switching device operable to switchably connect the output of a random signal generator to the calibration capacitor and further to each of the plurality of DAC capacitors, such that when a random signal from the random signal generator is applied to the calibration capacitor and further to each of the plurality of DAC capacitors, respectively, the output from the digital to analog converter is indicative of the gain of the calibration capacitor and further each of the plurality of DAC capacitors, respectively.

15. The analog to digital converter of claim 14, further comprising:

a sample and hold circuit with an output;

a subtractor operably connected to receive the output of the sample and hold circuit and the output of the digital to analog converter and operable to subtract the output of the digital to analog converter from the output of the sample and hold circuit in order to generate a remainder;

an amplifier operably connected to receive the remainder and operable to amplify the remainder to generate an amplified remainder; and

a calibration unit operable to receive the amplified remainder and to determine information representative of the gain of the calibration capacitor and further each of the plurality of DAC capacitors, respectively, when a random signal from the random signal generator is applied to the calibration capacitor and further to each of the plurality of DAC capacitors, respectively.

16. The analog to digital converter of claim 15, wherein the calibration unit is further operable to determine information representative of a mean value of the determined information representative of the gains of each of the plurality of DAC capacitors, the analog to digital converter further comprising:

a comparator operable to receive the analog signal and a reference signal, the comparator operable to compare the analog signal to the reference signal and to generate a digital output value based upon the comparison;

a weighting unit operable to receive the digital output value from the comparator and the information representative of the determined mean value from the calibration unit, and operable to multiply the digital output value with the information representative of determined mean value to generate a weighted digital output value based upon the multiplication.

17. The analog to digital converter of claim 16, wherein the calibration unit is further operable to determine information representative of the differences between the determined information representative of the gain of each of the plurality of DAC capacitors and the calibration capacitor to generate information representative of a DAC error, the analog to digital converter further comprising:

a digital output subtractor operably connected to receive the weighted digital output from the weighting unit and the information representative of the DAC error, and to subtract the information representative of the DAC error from the weighted digital output in order to generate a transfer error compensated digital output value based upon the subtraction.

18. The analog to digital converter of claim 15, wherein the calibration unit further comprises:

a flow controller operably connected to the switching device and operable to switchably connect the output of a random signal generator to the calibration capacitor and further to each of the plurality of DAC capacitors.