Clamp circuit for clamping a digital video signal

• US 7,095,452 B2
• Filed: 10/31/2003
• Issued: 08/22/2006
• Est. Priority Date: 01/08/2003
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Tachibana, Masanori
• Primary Examiner(s): Yenke, Brian P.
• Application Number:
  US10/697,332
• Publication Number:
  US 20040130375A1
• Time in Patent Office: 1,026 Days
• Field of Search: 348/687, 348/689, 348/690, 348/691, 348/257
• US Class Current: 348/691
• CPC Class Codes: H03G 11/00 Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
• CPC Class Codes: H04N 5/18 by means of "clamp" circuit operated by switching circuit

Abstract

A clamp control circuit outputs a clamp control signal after a delay of a predetermined time if a digital video signal is detected. A sampling circuit that extracts sampling data of a pedestal level from a luminance corrected signal based on a clamp pulse at a timing of the back porch. A data averaging circuit calculates an average of the sampling data of the pedestal level. A data holding circuit holds a difference between the average and a digital signal processing reference level when the clamp control signal is output and also when the clamp control signal is not output. A level correction circuit corrects a level of the luminance signal based on the difference held by the data holding circuit and outputs the corrected luminance signal.

Claims

1. A clamp circuit comprising:

a converter that converts an input analog video signal to a digital video signal;

a separation unit that separates a chroma signal and a luminance signal from the digital video signal;

a clamp control circuit that monitors the digital video signal and outputs a clamp control signal in response to a monitoring result of the digital video signal after a predetermined time for extracting a pedestal level inserted in a back porch included in a horizontal banking interval of the analog video signal has elapsed; and

a clamp processing circuit that,

while the clamp control circuit does not output the clamp control signal, extracts the pedestal level from a corrected luminance signal output from the clamp processing circuit, conducts computation processing to converge the extracted pedestal level to a digital signal processing reference level, and corrects the luminance signal input to said clamp processing circuit based on a result of the computation processing to output the corrected luminance signal, and

once the clamp control circuit outputs the clamp control signal, holds a result of the computation processing at the time the clamp control circuit outputs the clamp control signal, and corrects the luminance signal input to said clamp processing circuit based on the held result to output the corrected luminance signal.

2. The clamp circuit according to claim 1, wherein the clamp control circuit comprises:

a signal detection circuit that monitors a change in the digital video signal and outputs a signal detection signal, upon detecting that the digital video signal has changed; and

a delay circuit that delays the signal detection signal by the predetermined time and outputs the delayed signal detection signal as the clamp control signal.

3. The clamp circuit according to claim 1, wherein the clamp control circuit comprises:

a synchronization detection circuit that outputs a synchronization detection signal, upon detecting a horizontal synchronizing signal from the digital video signal; and

a delay circuit that delays the synchronization detection signal by the predetermined time and outputs the delayed synchronization detection signal as the clamp control signal.

4. The clamp circuit according to claim 1, wherein the clamp control circuit comprises:

a synchronization detection circuit that outputs a synchronization detection signal, upon detecting a vertical synchronizing signal from the digital video signal; and

a delay circuit that delays the synchronization detection signal by the predetermined time and outputs the delayed synchronization detection signal as the clamp control signal.

5. The clamp circuit according to claim 1, wherein the clamp control circuit comprises:

a synchronization detection circuit that outputs a synchronization detection signal, upon detecting a horizontal synchronizing signal from the input analog video signal; and

a delay circuit that delays the synchronization detection signal by the predetermined time and outputs the delayed synchronization detection signal as the clamp control signal.

6. The clamp circuit according to claim 1, wherein the clamp control circuit comprises:

a synchronization detection circuit that outputs a synchronization detection signal, upon detecting a vertical synchronizing signal from the input analog video signal; and

a delay circuit that delays the synchronization detection signal by the predetermined time and outputs the delayed synchronization detection signal as the clamp control signal.

7. The clamp circuit according to claim 1, wherein the clamp processing circuit comprises:

a sampling circuit that extracts sampling data of a pedestal level from a corrected luminance signal based on a clamp pulse input to said sampling circuit at timing of the back porch;

a data averaging circuit that calculates an average of the sampling data of the pedestal level;

a calculating circuit that calculates a difference between the digital signal processing reference level and the average;

a data holding circuit that holds and provides the difference when the clamp control circuit outputs the clamp control signal and provides the difference when the clamp control circuit does not output the clamp control signal; and

a level correction circuit that corrects a level of the luminance signal input to said clamp processing circuit based on the difference provided by the data holding circuit to output the corrected luminance signal.