Method and circuit for reducing defect current from array element failures in random access memories

• US 7,095,642 B1
• Filed: 03/12/2004
• Issued: 08/22/2006
• Est. Priority Date: 03/27/2003
• Status: Expired due to Fees

• Current Assignee: Acacia Research Group LLC (Acacia Research Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Parent, Richard, Chapman, David
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/799,742
• Time in Patent Office: 893 Days
• Field of Search: 365/225.7, 365/96, 365/200
• US Class Current: 365/51
• CPC Class Codes: G11C 29/83 with reduced power consumption

Abstract

A defect current contribution elimination technique may be suitable for dynamic random access memories (DRAMs) and other memory devices. A defect current can be eliminated by using an isolation circuit (106) between bitlines (102-0 and 102-1) and an associated sense amplifier circuit (104). Isolation circuit (106) can be controlled by programmable elements, such as fusible links, which are blown at wafer test to isolate the defective bitlines from the sense amplifier circuit. Isolated, defective bitlines may initially float, but based upon the type of defect, such bitlines can be resistively tied to another element, and as a result no DC current will flow. According to another implementation, controllable devices are placed between wordlines (206) and the wordline driver circuits (226-y). A current path through a defective wordline can be similarly cut-off.

Claims

1. A memory circuit, comprising:

a plurality of sense amplifier circuits having a predetermined pitch in a first direction; and

a plurality of programmable element controlled devices, each programmable element controlled device fitting within the pitch and isolating at least one associated bitline from a corresponding sense amplifier circuit when disabled.

2. The memory circuit of claim 1, wherein:

the programmable element controlled devices comprise n-channel insulated gate field effect (IGFET) transistors laid-out within the pitch of the corresponding sense amplifier.

3. The memory circuit of claim 2, wherein:

each of programmable element controlled devices includes

a first n-channel IGFET having a source-drain path coupled between a first bitline of a bitline pair and the corresponding sense amplifier circuit, and

a second n-channel IGFET having a source-drain path coupled between a second bitline of the bitline pair and the corresponding sense amplifier circuit.

4. The memory circuit of claim 1, wherein:

each bitline is coupled to a plurality of memory cells selected from the group consisting of one transistor dynamic random access memory (DRAM) type cells, magnetoresistive RAM (MRAM) cells, thyristor RAM (TRAM) cells, and ferromagnetic RAM (FRAM) cells.

5. The memory circuit of claim 1, wherein;

the bitlines comprise folded bitline pairs, each bitline of a bitline pair being arranged parallel and adjacent to one another.

6. The memory circuit of claim 1, wherein:

the bitlines comprise open bitline pairs, with one bitline of each pair extending over one array section and the other bitline of each pair extending over a different array section.

7. The memory circuit of claim 1, wherein:

the bitlines comprise unpaired bitlines, each coupled to a sense amplifier circuit that also receives a reference value to compare with a data signal provided by each bitline.

8. The memory circuit of claim 1, wherein:

the bitlines are arranged into logical groups each including a plurality of bitline pairs; and

the programmable element controlled devices associated with each logical group are commonly disabled in response to the same control signal.

9. A circuit for reducing defect induced standby current in a memory device, comprising:

a plurality of first conductive lines parallel to one another, each first conductive line coupled to a plurality of memory cells in a memory cell array;

a plurality of first circuits arranged on at least one side of the memory array, each first circuit being associated with at least one associated first conductive line and having a same first pitch in a first direction; and

a plurality of first isolation circuits, each first isolation circuit permanently isolating a corresponding first circuit from the associated at least one first conductive line when activated and fitting within the first pitch.

10. The circuit of claim 9, wherein:

the plurality of first conductive lines comprise bitlines commonly coupled to memory cells of the same column in the memory cell array; and

the plurality of first circuits comprise sense amplifier circuits for driving an associated bitline according to a data value on such bitline.

11. The circuit of claim 10 further including:

a plurality of wordlines parallel to one another, each wordline coupled to memory cells of the same row;

a plurality of wordline driver circuits arranged on at least a second side of the memory array, each wordline driver circuit coupled to at least one of the wordlines and having the same pitch in a second; and

a plurality of second isolation circuits, each second isolation circuit permanently isolating a corresponding wordline driver circuit from the associated wordline when activated.

12. The circuit of claim 9, wherein:

the plurality of first conductive lines comprise wordlines commonly coupled to memory cells of the same row in the memory cell array; and

the plurality of first circuits comprises wordline driver circuits for driving an associated wordline according to an applied address value.

13. The circuit of claim 9, further including:

at least one fuse circuit for providing an activation signal according to the state of at least one fuse-type element; and

each isolation circuit comprises at least one transistor having a gate coupled to the activation signal.

14. The circuit of claim 13, wherein:

the isolation circuit includes a plurality of transistors having gates commonly coupled to the activation signal.

15. The circuit of claim 13, wherein:

the fuse-type element is selected from the group consisting of;

a fusible link alterable to have a conducting or a non-conducting state, an anti-fuse structure alterable to have a conducting or a non-conducting state, an electrically programmable memory cell programmable to have a conducting or a non-conducting state.