Apparatus and method for trellis encoding data for transmission in digital data transmission systems

• US 7,095,707 B2
• Filed: 01/12/2001
• Issued: 08/22/2006
• Est. Priority Date: 08/25/1995
• Status: Expired due to Fees

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Terayon Communications Systems Incorporated (Motorola Solutions, Inc.)
• Inventors: Azenkot, Yehuda, Rakib, Selim Shlomo
• Primary Examiner(s): Sam, Phirin
• Application Number:
  US09/759,842
• Publication Number:
  US 20020015423A1
• Time in Patent Office: 2,048 Days
• Field of Search: 370/204, 370/206, 370/207, 370/208, 370/209, 370/335, 370/342, 375/215, 375/222, 375/261, 375/265, 375/296
• US Class Current: 370/204
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/39 Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H04B 1/1027 assessing signal quality or detecting noise/interference for the received signal
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/7087 Carrier synchronisation aspects
• CPC Class Codes: H04B 2201/709709 Methods of preventing interference
• CPC Class Codes: H04B 7/2668 Arrangements for Wireless Code-Division Multiple Access [CDMA] System Synchronisation, for code acquisition H04B1/7075, for code tracking H04B1/7085
• CPC Class Codes: H04H 20/77 using carrier waves
• CPC Class Codes: H04H 20/78 CATV [Community Antenna Television] systems
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713
• CPC Class Codes: H04J 13/004 Orthogonal
• CPC Class Codes: H04J 14/007 Orthogonal Optical Code Multiplex
• CPC Class Codes: H04J 3/0602 Systems characterised by the synchronising information used
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04J 3/0638 Clock or time synchronisation among nodes; Internode synchronisation synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/16 in which the return channel carries supervisory signals, e.g. repetition request signals
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 2025/03414 : Multicarrier
• CPC Class Codes: H04L 2027/0083 : Signalling arrangements
• CPC Class Codes: H04L 2027/0087 : Out-of-band signals, (e.g. pilots)
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03343 : Arrangements at the transmitter end
• CPC Class Codes: H04L 25/4921 : using quadrature encoding, e.g. carrierless amplitude-phase coding
• CPC Class Codes: H04L 27/0014 : Carrier regulation of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657
• CPC Class Codes: H04L 27/2656 : Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
• CPC Class Codes: H04L 27/2657 : Carrier synchronisation
• CPC Class Codes: H04L 27/2662 : Symbol synchronisation
• CPC Class Codes: H04L 27/362 : Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence
• CPC Class Codes: H04L 5/023 : Multiplexing of multicarrier modulation signals multicarrier modulation H04L27/2601
• CPC Class Codes: H04L 5/026 : using code division
• CPC Class Codes: H04L 5/06 : the signals being represented by different frequencies combined with time-division multiplexing H04L5/26
• CPC Class Codes: H04L 7/041 : using special codes as synchronising signal
• CPC Class Codes: H04N 21/2221 : being a cable television head-end CATV in broadcast systems H04H20/78
• CPC Class Codes: H04N 21/2408 : Monitoring of the upstream path of the transmission network, e.g. client requests monitoring data switching networks utilization H04L43/0876; scheduling or organising the servicing of application requests H04L67/60
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4383 : Accessing a communication channel
• CPC Class Codes: H04N 7/10 : Adaptations for transmission by electrical cable H04N7/12 takes precedence
• CPC Class Codes: H04N 7/17309 : Transmission or handling of upstream communications
• CPC Class Codes: H04N 7/54 : the signals being synchronous H04N21/23602, H04N21/23614, H04N21/2365, H04N21/2368, H04N21/4341, H04N21/4342, H04N21/4347, H04N21/4348 take precedence
• CPC Class Codes: H04W 24/00 : Supervisory, monitoring or testing arrangements
• CPC Class Codes: H04W 48/16 : Discovering, processing access restriction or access information
• CPC Class Codes: H04W 56/00 : Synchronisation arrangements
• CPC Class Codes: H04W 74/0866 : using a dedicated channel for access

Abstract

A system for bidirectional communication of digital data between a central unit and a remote unit wherein the need for tracking loops in the central unit has been eliminated. The central unit transmitter generates a master carrier and a master clock signal which are used to transmit downstream data to the remote units. The remote units recover the master carrier and master clock and synchronize local oscillators in each remote unit to these master carrier and master clock signals to generate reference carrier and clock signals for use by the remote unit receiver. These reference carrier and clock signals are also used by the remote unit transmitters to transmit upstream data to the central unit. The central unit receiver detects the phase difference between the reference carrier and clock signals from the remote units periodically and adjusts the phase of the master carrier and master clock signals for use by the central unit receiver to receive the upstream data.

Claims

1. A Trellis encoder for encoding payload data bits with redundant bits and mapping the resulting bits into a constellation point, comprising:

a plurality of payload data inputs for receiving a plurality of payload bits;

a convolutional encoder having a plurality of inputs coupled directly to a plurality of said payload data inputs and a first output and a second output;

a separate exclusive OR gate having an input coupled to one of said payload data inputs and having an input coupled to said first output of said convolutional encoder and having an output;

a mapper having a plurality of inputs coupled directly to a plurality of said payload data inputs, and having an input coupled to said second output of said convolutional encoder, and having an input coupled to said output of said exclusive OR gate, and having a plurality of I outputs and a plurality of Q outputs at which signals appear which are constellation points in a quadrature amplitude modulated constellation which are derived from said payload data appearing at said payload data inputs.

2. The apparatus of claim 1 wherein said mapper functions to nonlinearly map the bits input thereto into a constellation point of a 16 QAM constellation.

3. The apparatus of claim 1 wherein three payload bits are received, and wherein said first and second payload bits are applied to said mapper in an unchanged state, and wherein said convolutional encoder is comprised of a chain of four D type flip flops, the first, second and third of which have their outputs coupled to the input of an exclusive OR gate which has its output coupled to the input of the next D flip flop in said chain, and the fourth flip-flop having its output coupled to an input of said mapper and to the input of said first flip flop, and wherein the exclusive OR gate between said first and second flip flops has an input coupled to receive said second payload bit, and wherein said exclusive OR gate between said second and third flip flops has an input coupled to receive said first payload bit and an additional input coupled to said output of said separate exclusive OR gate, and having an additional input coupled to the output of an AND gate which has a first input coupled to the output of said fourth flip flop and a second input coupled to the input of said fourth flip flop, and wherein said third payload bit is modified by said separate exclusive OR gate by exclusive OR combination with the output bit from said third flip flop of said convolutional encoder, and wherein said exclusive OR gate having an input coupled to the output of said third flip flop and an output coupled to the input of said fourth flip flop has an additional input coupled to said output of said exclusive OR gate and an additional input coupled to said output of said fourth flip flop.

4. The apparatus of claim 3 wherein said mapper at least one control input for receiving control signals which control whether said Trellis encoder operates in a normal mode wherein one redundant bit is added to each three payload bits or a fallback mode wherein the output of said mapper is divided into two symbols and transmitted separately with the two least significant bits (y0, y1) being transmitted as first symbol or constellation point in a QPSK 4 point constellation and the two most significant bits (y3, y2) being transmitted as a second symbol or constellation in a DQPSK constellation.

5. The apparatus of claim 1 wherein said convolutional encoder and separate exclusive OR gate are structured and coupled together to implement a 16 state convolutional encoding process which only allows certain predetermined patterns in the constellation points that are generated from said payload data bits.

6. The apparatus of claim 1 wherein said convolutional encoder and separate exclusive OR gate are structured and coupled together so as to be characterized by parity check polynomials given in octal form as follows:

h3=04, h2=10, h1=06, h0=23, d^2_free=5.O, Nfree=1.68, and wherein the nonlinear term is given by D^2[y0(S).AND.D^(−

1)y0(D)].

7. The apparatus of claim 1 wherein said mapper has multiple modes which add different numbers of redundant bits while always maintaining the code word length at 4 bits including a normal mode where one redundant bit is added per tribit, and a fallback mode which can be used when channel impairments are high wherein fewer payload bits are sent and more redundant bits are sent in each 4 bit code word.

8. An encoder for encoding payload data bits with redundant bits and mapping the resulting bits into a constellation point so as to achieve a coding gain, comprising:

first means for receiving a plurality of payload data bits and convolutionally encoding said payload bits to generate at least one additional bit derived mathematically from a Boolean logic combination of said payload bits, and for outputting at least some of said payload bits unchanged and at least one of said payload bits as modified by a logical operation with a bit output from an intermediate stage of a convolutional encoding process carried out in said first means, and outputting a final bit resulting from said convolutional encoding process; and

second means coupled to receive one or more mode control signals and coupled to receive said final bit from said convolutional encoding process and said unchanged payload bits and said payload bit after modification by said convolutional encoding process, for mapping said bits into a constellation point of a constellation of possible data points, each point defined by a value on a real axis and a value on an imaginary axis, said mapping having at least a normal mode and a fallback mode.

9. The encoder of claim 8 wherein said first means includes a 16-state convolutional encoder characterized by parity check polynomials given in octal form as follows:

h3=04, h2=10, h1=06, h0=23, d^2_free=5.O, Nfree=1.68 and wherein the nonlinear term is given by D^2[y0(S).AND.D^(−

1)y0(D)].

10. The encoder of claim 8 wherein said first means and second means implement a forward error correction encoder state machine or lookup table coupled to a state memory which adds at least one extra bit to provide redundancy for error detection and correction and for use by a Viterbi Decoder in a receiver for ascertaining with greater accuracy the data that was actually sent despite the presence of noise, said at least one extra bit providing a constellation that is bigger than the constellation would have without said extra bit(s) thereby enabling more spacing between constellation points thereby enabling better discrimination between points by the receiver and lowering the bit error rate without increasing the bandwidth.

11. A process for Trellis encoding a plurality of payload bits into a constellation point, comprising:

receiving a plurality of payload bits;

convolutionally encoding a combination of said payload bits into one or more additional bits by applying said payload bits to different inputs of a convolutional encoder and also applying a modified bit to an input of said convolutional encoder, said modified bit being generated by exclusive-ORing one of said payload bits with an output bit from an intermediate stage of said convolutional encoder, said convolutional encoding step resulting in output of one or more additional bits; and

mapping the combination of at least some of said payload bits in an unmodified state, said modified bit and said one or more additional bits into a constellation point, wherein said process for Trellis encoding is performed upon multiple pluralities of said payload bits successively, and wherein said step of convolutional encoding comprises introducing a certain dependency between successive constellation points generated from said successive plurality of payload bits such that only certain patterns or permissible sequences of constellation points are permitted, said patterns or permissible sequences capable of being modelled in a receiver'"'"'s Viterbi decoder as a Trellis code.

12. A process for Trellis encoding a plurality of payload bits into a constellation point, comprising:

receiving a plurality of payload bits;

convolutionally encoding a combination of said payload bits into one or more additional bits by applying said payload bits to different inputs of a convolutional encoder and also applying a modified bit to an input of said convolutional encoder, said modified bit being generated by exclusive-ORing one of said payload bits with an output bit from an intermediate stage of said convolutional encoder, said convolutional encoding step resulting in output of one or more additional bits; and

mapping the combination of at least some of said payload bits in an unmodified state, said modified bit and said one or more additional bits into a constellation point, wherein said step of mapping includes the steps of receiving a control signal that indicates whether a normal mode or a fallback mode is to be implemented wherein said normal mode maps said plurality of payload bits, said modified bit and said one or more additional bits into a constellation point in a constellation of points that is larger than a constellation of possible points would be if only the original payload bits were mapped into a constellation, and said fallback mode mapping said plurality of bits in an unmodified payload state, said modified bit and said one or more additional bits into a constellation point in a constellation of points that is larger than the constellation of points that are possible in said normal mode.

13. A process for Trellis encoding a plurality of payload bits into a constellation point, comprising:

receiving a plurality of payload bits;

convolutionally encoding a combination of said payload bits into one or more additional bits by applying said payload bits to different inputs of a convolutional encoder and also applying a modified bit to an input of said convolutional encoder, said modified bit being generated by exclusive-ORing one of said payload bits with an output bit from an intermediate stage of said convolutional encoder, said convolutional encoding step resulting in output of one or more additional bits; and

mapping the combination of at least some of said payload bits in an unmodified state, said modified bit and said one or more additional bits into a constellation point, wherein the step of convolutionally encoding is characterized by parity check polynomials given in octal form as follows;

h3=04, h2=10, h1=06, h0=23, d^2_free=5.0, Nfree=1.68, and wherein the nonlinear term is given by D^2[y0(S).AND.D^(−

1)y0(D)].