Synchronous flash memory with status burst output

• US 7,096,283 B2
• Filed: 04/26/2004
• Issued: 08/22/2006
• Est. Priority Date: 07/28/2000
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US10/831,823
• Publication Number:
  US 20040199713A1
• Time in Patent Office: 848 Days
• Field of Search: 710/28, 710/29, 710/33, 710/35, 710/39, 710/52, 710/53, 710/58, 710/60, 710/61, 710/74, 710/7, 710/11, 710/16, 710/14, 710/18, 710/19, 711/1, 711/5, 711/6, 711/103, 711/109, 711/167, 711/169
• US Class Current: 710/14
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Claims

1. Amethod of operating a synchronous memory device comprising:

establishing a read burst length of x-cycles in a mode register such that data output from a status register of the synchronous memory device is output on x-consecutive clock cycles;

initiating a register read operation to read data stored in the status register; and

outputting data stored in the status register on external data connections for x-consecutive clock cycles;

wherein the mode register is used to define the specific operation of the synchronous memory device including selecting at least one of a burst length, a burst type, a CAS latency, and an operating mode, and wherein the status register allows an external processor to monitor the status of an internal state machine during write, erase, and protect operations.

2. The method of claim 1 further comprises establishing a clock latency of y-cycles, such that the data stored in the status register is output y-clock cycles following the initiation of the register read.

3. The method of claim 1 wherein the status register contains non-array data such as operating data, status data, manufacture identification, or memory device identification.

4. Amethod of operating a synchronous memory device comprising:

receiving a read status register command; and

outputting status register data from the synchronous memory device in response to the read register command for x-clock cycles;

wherein the status register allows an external processor to monitor the status of an internal state machine during write, erase, and protect operations.

5. The method of claim 4 wherein the synchronous memory device is a synchronous flash memory device having non-volatile memory cells.

6. The method of claim 4 wherein the status register data is output y-clock cycles after receiving the read register command.

7. The method of claim 4 wherein the status register data comprises non-array data such as operating data, status data, manufacture identification, or memory device identification.

8. The method of claim 4 wherein x-clock cycles is selected from either 2, 4, 8 or 16 clock cycles.

9. Amethod of reading register data in a synchronous memory device comprising:

providing a status register read command from a processor to the memory device;

receiving the register read command on an input of the memory device on a first clock cycle;

reading status register data stored in a memory register;

outputting the status register data during a plurality of clock cycles on data communication connections of the synchronous memory device, wherein outputting the status register data is delayed for a predefined clock latency period after receiving the register read command;

wherein the status register allows an external processor to monitor the status of an internal state machine during write, erase, and protect operations.

10. The method of claim 9 wherein the status register data comprises non-array data such as operating data, status data, manufacture identification, or memory device identification.

11. The method of claim 9 further comprises:

setting a burst length of the synchronous memory device to define the plurality of clock cycles that the status register data is output; and

setting a clock latency period.

12. The method of claim 11 wherein the burst length is selected from either 2, 4, 8 or 16 clock cycles.

13. The method of claim 9 wherein the synchronous memory device is a synchronous flash memory device having non-volatile memory cells.

14. Amethod of operating a synchronous memory device, comprising:

programming a status read register with a burst length setting and clock latency setting;

placing the memory in a status register read mode; and

outputting non-array data from a status register for a series of clock cycles according to the read register programming;

wherein the status register allows an external processor to monitor the status of an internal state machine during write, erase, and protect operations.

15. The method of claim 14, wherein outputting further comprises:

controlling status register data output using the burst length setting and the clock latency setting of the programming.

16. The method of claim 14, and further comprising:

providing a memory status signal from the status register upon initiation of a status read command.

17. The method of claim 14, wherein the burst length setting is four words and the clock latency setting is three cycles.