Communications interface for enabling extension of an internal common bus architecture (CBA)

• US 7,096,301 B2
• Filed: 03/06/2003
• Issued: 08/22/2006
• Est. Priority Date: 01/13/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Karguth, Brian, Kennedy, James H., Beaudoin, Denis R.
• Primary Examiner(s): Cottingham, John R.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US10/382,679
• Publication Number:
  US 20040139262A1
• Time in Patent Office: 1,265 Days
• Field of Search: 710300-306, 710 2- 4, 710 8- 19, 710 24- 26, 710 36- 38, 710/31, 710312-316, 710/268, 710 48- 51, 710/105
• US Class Current: 710/305
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion

Abstract

A serial communications interface is described that enables the extension of an internal Communications Bus Architecture (CBA) bus segment to one or more external devices. The interface accomplishes this function by serializing bus transactions in one device, transferring the serial transaction between devices via one interface port, and de-serializing the transaction in the external device. The general features include low pin count (as few as three signals), simple packet based transfer protocol for memory mapped access, symmetric operation, simple block code formatting, supports both host to peripheral and peer to peer transactions, and support multiple outstanding transactions.

Claims

1. A communications system for enabling extension of an internal common bus architecture (CBA) bus segment of a first physical semiconductor chip device to an internal CBA bus segment of a second external physical semiconductor chip device comprising:

a first serial communications interface module in said first semiconductor chip device of varying bit width at transmit and receive pins coupled to said internal bus segment of said first semiconductor chip device for serializing bus transaction from said first device to an output port of said first device;

a second serial communications interface module in said second semiconductor chip external device of varying bit width at transmit and receive pins coupled to said internal bus segment for said second semiconductor chip device for de-serializing data received at an input port for said second device for providing an extension of said internal CBA bus segment in said second device to external physical devices at an input port and

an external serial connector for transferring the serialized transaction between first and second devices at said input and output ports using semiconductor chip protocols;

said modules carrying CBA bus commands, interrupt and confimiration operations in band over the same transmit and receive pins.

2. The system of claim 1 wherein multiple outstanding CBA bus transactions are sent and received.

3. The system of claim 1 wherein said second serial communications interface module in said second external device is daisy chain coupled between said internal bus segment of said second device and other peripheral devices through external serial cablings.

4. A communications system for enabling extension of an internal common bus architecture (CBA) segment of a first physical device to an internal CBA bus segment of a second external physical device comprising:

a first serial communications interface module of varying bit width at transmit and receive pins in said first device coupled between said internal bus segment of said first device and an input and output port of said first device for serializing bus transactions from said first device and said output port of said first device and de-serializing data received at said input port of said first device;

a second serial communications interface module of varying bit width at transmit and receive pins in said second external device coupled between said internal bus segment of said second device and an input and output port of said second device for serializing bus transactions from said second device and said output port of said second device and de-serializing data received at said input port of said second device; and

an external serial connector coupled to said input and output ports of said first and second devices for transferring the serialized transaction between first and second devices;

said modules carrying CBA bus commands, interrupt and configuration operations in band over the same connections and said modules providing serial width negotiation between said modules.

5. The system of claim 4 wherein said second serial communications interface module in said second external device is daisy chain coupled between said internal bus segment of said second device and other peripheral devices through external serial cablings.

6. The system of claim 4 wherein said first and second modules each provide address translation between devices.

7. The system of claim 4 wherein a width detection mechanism is used.

8. The system of claim 4 wherein said modules will send out width negotiation protocol to determine the width at the transmit and receive pins.

9. The system of claim 4 wherein said first and second modules each provide a set of registers.

10. The system of claim 6 wherein said first and second modules include encoding and decoding.

11. A communications system for enabling extension of an internal common bus architecture (CBA) segment of a first physical device to an internal CBA bus segment of a second external physical device comprising:

a first serial communications interface module in said first device coupled between said internal bus segment of said first device and an input and output port of said first device for serializing bus transactions from said first device and said output port of said first device and de-serializing data received at said input port of said first device;

a second serial communications interface module in said second external device coupled between said internal bus segment of said second device and an input and output port of said second device for serializing bus transactions from said second device and said output port of said second device and de-serializing data received at said input port of said second device; and

an external serial cable coupled to said input and output ports of said first and second devices for transferring the serialized transaction between first and second devices;

said first and second modules each provide outbound and inbound command First In First Out (FIFO) registers and return data FIFO registers.

12. A communications system for enabling extension of an internal common bus architecture (CBA) segment of a first physical device to an internal CBA bus segment of a second external physical device comprising:

a first serial communications interface module in said first device coupled between said internal bus segment of said first device and an input and output port of said first device for serializing bus transactions from said first device and said output port of said first device and de-serializing data received at said input port of said first device;

a second serial communications interface module in said second external device coupled between said internal bus segment of said second device and an input and output port of said second device for serializing bus transactions from said second device and said output port of said second device and de-serializing data received at said input port of said second device; and

an external serial cable coupled to said input and output ports of said first and second devices for transferring the serialized transaction between first and second devices;

said first and second modules each provide a set of resisters;

said set of registers includes a control register for controlling the module, transmit address map register and receive address map registers for address translation.

13. The system of claim 12 wherein said set of registers includes an interrupt pending/set register, an interrupt status/clear register, a priority vector status/clear register and interrupt pointer register.