Method and apparatus for accelerating detection of serial bus device speed signals

• US 7,096,302 B2
• Filed: 12/21/2004
• Issued: 08/22/2006
• Est. Priority Date: 11/16/1999
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Duckwall, William S.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US11/021,338
• Publication Number:
  US 20050114582A1
• Time in Patent Office: 609 Days
• Field of Search: None
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

A method and apparatus for accelerating detection of speed code signals, and in particular S400 signals, for IEEE Standard 1394-1995 serial bus devices. The present invention validates S400 mode immediately after detecting an S400 speed signal, or immediately after detecting an S400 speed signal following a first S200 speed signal. The invention further provides S200 and S100 mode validation according to current implementations. Additionally, the invention does not require RX_DATA_PREFIX as a pre-requisite for signal detection.

Claims

1. A computer-readable medium containing instructions which, when executed by a computer, administer a serial bus, by

receiving a first speed signal by a speed signal register, the first speed signal indicating a first speed code;

receiving a second speed signal by the speed signal register, the second speed signal indicating a second speed code; and

validating a speed mode based on the order in which the speed signals were received.

2. The computer readable medium of claim 1, wherein the first speed signal is a S200 signal and the second speed signal is an S400 signal, and the speed mode validated is an S400 speed mode.

3. The computer-readable medium of claim 1, further comprising instructions that execute to clear the speed signal register after transmission of a plurality of packets has concluded.

4. The computer-readable medium of claim 1, further comprising instructions that execute to clear the speed signal register after a chip reset has occurred.

5. The computer-readable medium of claim 1, further comprising instructions that execute to clear the speed signal register after a self-ID speed signal trap has occurred.