Instruction processor write buffer emulation using embedded emulation control instructions

• US 7,096,322 B1
• Filed: 10/10/2003
• Issued: 08/22/2006
• Est. Priority Date: 10/10/2003
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Williams, James A., Sollom, Jason D.
• Primary Examiner(s): Ellis, Kevin L.
• Application Number:
  US10/683,028
• Time in Patent Office: 1,047 Days
• Field of Search: 711/137, 711/143, 711/154
• US Class Current: 711/143
• CPC Class Codes: G06F 8/4442 Reducing the number of cache misses; Data prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

Abstract

Techniques are described for accurately and efficiently emulating an instruction processor having a write buffer. The described techniques may be utilized to quickly develop an emulated instruction processor that provides a fully-functional write buffer interface in an efficient and elegant manner. For example, a system is described that includes a computing system that provides an emulation environment, and software executing within the emulation environment that emulates an instruction processor having a write buffer interface and a memory interface. The software emulates the instruction processor by selectively outputting a write request on the write buffer interface or the memory interface in response to an emulation control instruction embedded within an instruction stream.

Claims

1. A processor-based method comprising:

processing an emulation control instruction with an emulated instruction processor to set a state of a pre-fetch control bit within the emulated instruction processor, wherein the emulated instruction processor has a write buffer interface and a memory interface; and

processing a write instruction with the emulated processor to selectively output a write request via the write buffer interface or the memory interface based on the state of the pre-fetch control bit.

2. The method of claim 1, wherein the memory architecture includes a cache and the memory interface comprises a cache interface.

3. The method of claim 2, wherein selectively outputting a write request comprises outputting the write request via the write buffer interface to reserve ownership of one or more cache lines within the cache.

4. The method of claim 3, further comprising:

processing a second emulation control instruction with the emulated instruction processor to set a state of a cache control bit within the emulated instruction processor; and

outputting a cache control line when issuing the write request as a function of the state of the cache control bit.

5. The method of claim 4, wherein outputting a cache control line comprises:

outputting the cache control line to direct the cache to operate as a leaky cache when the state of the cache control bit is a first state; and

outputting the cache control line to direct the cache to operate as a write-back cache when the state of the cache control bit is a second state different from the first state.

6. The method of claim 1, further comprising:

compiling test software to produce an instruction stream that includes the write request; and

inserting the emulation control instruction into the instruction stream during compilation to direct the emulated instruction processor to emulate write buffer functionality with the write buffer interface.

7. The method of claim 1, further comprising:

compiling test software to produce an instruction stream for processing by the emulated instruction processor, wherein the instruction stream includes the write request; and

inserting the emulation control instruction into the instruction stream during compilation and earlier in the instruction stream than the write request to enable write pre-fetching.

8. The method of claim 7, further comprising inserting a duplicate of the write instruction followed by a second emulation control instruction into the instruction stream after the first emulation control instruction, wherein the a second emulation control instruction disables write pre-fetching so that the emulated instruction processor outputs a write request associated with the duplicate write instruction via the write buffer interface and the write request associated with the non-duplicate write instruction via the memory interface.

9. The method of claim 7, further comprising modifying a non-emulated component based on the processing of the instruction stream by the emulated instruction processor.

10. The method of claim 9, wherein the non-emulated component comprises a memory architecture.

11. The method of claim 7, further comprising modifying the test script based on the processing of the instruction stream by the emulated instruction processor.

12. A processor-based method comprising:

compiling test software to output an instruction stream for execution by for an emulated instruction processor;

processing the instruction stream during compilation to insert one or more instructions into the instruction stream to direct the emulated instruction processor to output pre-fetch write requests out a write buffer interface upon execution of the instruction stream.

15. The method of claim 12, further comprising processing the instruction stream during compilation to further insert an emulation control instruction into the instruction stream to direct the emulated instruction processor to control a cache control line associated with the pre-fetch write requests.

16. The method of claim 12, wherein the cache control line directs a cache to selectively operate as a write-back cache or a write through cache when processing the pre-fetch write requests.

13. The method of clam 12, wherein processing the instruction stream during compilation comprises:

identifying a first write instruction within the instruction stream;

generating a set of instructions including;

(a) a first emulator control instruction to enable a pre-fetch mode of the emulated processor;

(b) a second write instruction following the first emulator control instruction to cause the emulated instruction processor to output a write request out the write buffer interface, and

(c) a second emulator control instruction following the second write instruction to disable the pre-fetch mode;

inserting the generated set of instructions within the instruction stream prior to the first write instruction.

14. The method of claim 13, wherein the second write instruction is a duplicate of the first write instruction.

17. The method of clam 12, wherein processing the instruction stream during compilation comprises:

identifying a group of write instructions within the instruction stream;

inserting an emulator control instruction within the instruction stream prior to the group of write instructions to enable a pre-fetch mode of the emulated processor and direct the emulated processor to output write requests associated with the write instructions out the write buffer interface; and

inserting a branching type instruction within the instruction stream following the group of write instructions to direct the emulated instruction processor to re-execute the emulator control instruction and the group of write instructions to output the write requests associated with the write instructions out the memory interface.

18. A computer-implemented system for emulating write buffer operation comprising:

a computing system to provide an emulation environment; and

software executing within the emulation environment to emulate an instruction processor having a write buffer interface and a memory interface, wherein the software emulates the instruction processor by selectively outputting a write request on the write buffer interface or the memory interface in response to an emulation control instruction embedded within an instruction stream.

19. The system of claim 18, wherein the emulated instruction processor includes an emulation control register and a state machine, wherein the state machine processes the emulation control instruction and updates a pre-fetch control bit of the emulation control register to selectively enable or disable a pre-fetch mode for the emulated instruction processor.

20. The system of claim 19, further comprising a compiler executed by the computing system, wherein the compiler compiles test software to generate the instruction stream, and automatically inserts the emulator control instruction into the instruction stream to selectively enable or disable the pre-fetch mode of the emulated instruction processor.

21. The system of claim 20, wherein the compiler:

identifies a first write instruction within the instruction stream;

generates a set of instructions including (a) a first emulator control instruction to enable the pre-fetch mode of the emulated processor, (b) a second write instruction following the first emulator control instruction to cause the emulated instruction processor to output the write request out the write buffer interface, and (c) a second emulator control instruction following the write instruction to disable the pre-fetch mode; and

inserts the generated set of instructions within the instruction stream prior to the first write instruction.

22. The system of claim 20, wherein the compiler:

identifies a group of write instructions within the instruction stream;

inserts an emulator control instruction within the instruction stream prior to the group of write instructions to enable a pre-fetch mode of the emulated processor and direct the emulated processor to output write requests associated with the write instructions out the write buffer interface; and

inserts a branching type instruction within the instruction stream following the group of write instructions to direct the emulated instruction processor to re-execute the emulator control instruction and the group of write instructions to output the write requests associated with the write instructions out the memory interface.

23. The system of claim 18, wherein the software processes a second emulation control instruction embedded within the instruction stream and asserts a cache control line of the emulated instruction processor and associated with an attribute of the write request.

24. The system of claim 23, wherein the emulated instruction processor includes an emulation control register and a state machine, wherein the state machine processes the second emulation control instruction and updates a leaky control bit of the emulation control register to control whether a cache operates as a leaky cache or a write-back cache upon receiving the write request output by the emulated instruction processor.

25. A computer-implemented system for emulating write buffer operation comprising:

computing means for providing an emulation environment;

compiling means for compiling a test script to produce an instruction stream having at least one write instruction; and

processor emulating means for emulating an instruction processor having a write buffer interface and a memory interface, wherein the processor emulating means includes selecting means for outputting a write request on the write buffer interface or the memory interface in response to an emulation control instruction embedded within an instruction stream.

26. The system of claim 25, wherein processor emulating means comprises:

storing means for storing a pre-fetch control bit that enables a pre-fetch mode; and

controlling means for controlling the emulation control instruction and updating the pre-fetch control bit of the storing means.

27. The system of claim 25, wherein processor emulating means comprises:

storing means for storing a leaky control bit that enables a leaky mode that controls a state of a cache control line that directs a cache to operate as a leaky cache or a write-back cache upon receiving the write request output by the processor emulating means; and

controlling means for processing a second emulation control instruction of the instruction stream and updating the leaky control bit of the storing means.