Method and apparatus for diagonal routing by using several sets of lines

• US 7,096,448 B2
• Filed: 01/05/2002
• Issued: 08/22/2006
• Est. Priority Date: 01/19/2001
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Teig, Steven, Chao, Heng-Yi, Buset, Oscar
• Primary Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US10/040,915
• Publication Number:
  US 20030101428A1
• Time in Patent Office: 1,690 Days
• Field of Search: 716/11, 716/12, 716/13, 716/15, 716/16, 716/14
• US Class Current: 716/129
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/3953 detailed
• CPC Class Codes: G11B 7/08582 Sled-type positioners

Abstract

Some embodiments provide a method of routing nets within a region of an integrated-circuit (“IC”) layout. The method uses a first set of lines to partition the IC region into a plurality of sub-regions. In addition, the method uses a second set of lines to measure congestion of routes for the nets within the IC region. According to this method, at least some of the lines in the second set are different from the lines in the first set.

Claims

1. A method of routing sets of routable elements in a region of an integrated-circuit (“

IC”

) layout, the method comprising;

a) using a first set of lines to partition the IC region into a plurality of sub-regions;

b) defining at least one particular route for each particular routable elements, wherein each particular route for each particular set traverses the set of sub-regions that contain the set of routable elements;

c) using a second set of lines to measure congestion of routes within the IC region, wherein at least a plurality of the lines in the second set are different from the lines in the first set, wherein the second set of lines includes intersecting diagonal lines that form a diagonal grid, wherein the first set of lines includes intersecting horizontal and vertical lines that form a first rectilinear grid,

wherein the diagonal lines intersect at a center of the sub-regions created by the first set of lines.

2. A method of routing sets of routable elements within a region of an integrated-circuit (“

IC”

) layout, the method comprising;

a) partitioning the IC region into a plurality of sub-regions by using a first set of lines, wherein a plurality of diagonal routing paths exist between the sub-regions;

b) identifying the capacity of diagonal routing paths based on a second set of lines, wherein at least a plurality of the lines in the second set are different from the lines in the first set; and

c) using the identified capacities to define routes for the sets of routable elements, wherein a particular route for a particular set of routable elements traverses the set of sub-regions that contain the set of routable elements.

3. The method of claim 2, wherein the second set of lines includes diagonal lines.

4. The method of claim 3, wherein the diagonal lines are at an angle of +A°

or −

A°

with respect to one of the axis of the IC region, wherein A is not 0 or 90, wherein the method uses the diagonal lines to identify the capacity of routing paths in ±

A°

directions between the sub-regions.

5. The method of claim 4, wherein A is 45.

6. The method of claim 4,

wherein the diagonal lines define a plurality of diagonal edges,

wherein each particular routing path intersects a particular diagonal edge,

wherein identifying the capacity of the diagonal routing paths comprises deriving each particular diagonal routing path'"'"'s capacity from the size of the particular diagonal edge intersected by the particular diagonal routing path.

7. The method of claim 2, wherein each routing path is defined with respect to a particular wiring layer and each layer has a particular pitch, wherein identifying the capacity of the diagonal routing paths further comprises using the pitch of each particular routing path'"'"'s layer to derive the particular routing path'"'"'s capacity.

8. The method of claim 7 further comprising:

hierarchically partitioning the region into smaller and smaller sub-regions;

specifying a route for each set of routable elements at each level of the hierarchy,

wherein the sub-regions at the lowest level of the hierarchy are Gcells,

wherein identifying the capacity of the diagonal routing paths at non-Gcell levels further comprises deriving the capacity of each particular diagonal routing path at non-Gcell levels from the number of tracks of wiring at the Gcell level in the direction of the particular routing path.

9. A method of routing a set of routable elements in a layout, the method comprising:

a) receiving a particular region of an integrated circuit (“

IC”

) layout,

b) partitioning said region into a plurality of sub-regions,

wherein a plurality of diagonal and non-diagonal routing paths exist between said sub-regions,

wherein the diagonal routing paths are defined with respect to a first grid, and the non-diagonal routing paths are defined with respect to a second grid; and

c) for the the set of routable elements, using at least one diagonal routing path and at least one non-diagonal routing path to define a route that connects the set of sub-regions that contain the set of routable elements.

10. The method of claim 9, wherein each routing path has a particular capacity, the method further comprising:

a) calculating the capacity of each particular diagonal routing path; and

b) calculating the capacity of each particular non-diagonal routing path.

11. The method of claim 10, wherein the capacity of the diagonal routing paths differ from the capacity of the non-diagonal routing paths.

12. The method of claim 10,

wherein the first grid includes a plurality of diagonal edges and the second grid includes a plurality of non-diagonal edges,

wherein each particular diagonal routing path intersects a particular diagonal edge, and each particular non-diagonal routing path intersect a particular non-diagonal edge,

wherein calculating each particular diagonal routing path'"'"'s capacity comprises deriving the particular diagonal routing path'"'"'s capacity from the size of the path'"'"'s corresponding diagonal edge,

wherein calculating each particular non-diagonal routing path'"'"'s capacity comprises deriving the particular non-diagonal routing path'"'"'s capacity from the size of the path'"'"'s corresponding non-diagonal edge.

13. The method of claim 12, wherein the sizes of the diagonal and non-diagonal edges differ.

14. The method of claim 12, wherein each particular diagonal edge connects the centers of a particular pair of sub-regions that are diagonally aligned with respect to each other.

15. The method of claim 12,

wherein said IC layout includes a plurality of interconnect-line layers, each layer having a particular pitch value,

wherein each particular routing path is on a particular one of said layers,

wherein calculating the capacity of each particular diagonal routing path comprises dividing the size of the diagonal edge intersected by the particular diagonal routing path by the pitch value of the path'"'"'s layer,

wherein calculating the capacity of each particular non-diagonal routing path comprises dividing the size of the non-diagonal edge intersected by the particular non-diagonal routing path by the pitch value of the path'"'"'s layer.

16. A method of routing a set of pins, within a particular region of an integrated circuit (“

IC”

) layout, according to an octagonal wiring model, the method comprising;

a) receiving the particular region of an integrated circuit (“

IC”

) layout,

b) partitioning said region into a plurality of four-sided sub-regions, wherein a plurality of ±

45°

diagonal and Manhattan routing paths exist between said sub-regions, wherein the Manhattan routing paths are defined with respect to a first grid, and the ±

45°

diagonal routing paths are defined with respect to a second grid that is at 45°

with respect to the first grid; and

c) using the diagonal and Manhattan routing paths to define a route that connects the set of sub-regions that contain the set of pins.

17. A computer readable medium comprising a computer program having executable code, the computer program for routing sets of routable elements within a region of an integrated-circuit (“

IC”

) layout, the computer program comprising;

a) a first set of instructions for partitioning the IC region into a plurality of sub-regions by using a first set of lines, wherein a plurality of diagonal routing paths exist between the sub-regions;

b) a second set of instructions for identifying the capacity of diagonal routing paths based on a second set of lines, wherein at least a plurality of the lines in the second set are different from the lines in the first set; and

c) a third set of instructions for using the identified capacities to define routes for the sets of routable elements, wherein a particular route for a particular set of routable elements traverses the set of sub-regions that contain the set of routable elements.

18. The computer readable medium of claim 17, wherein the second set of lines includes diagonal lines.

19. The computer readable medium of claim 18, wherein the diagonal lines are at an angle of +A°

or −

A°

with respect to one of the axis of the IC region, wherein A is not 0 or 90, wherein the second set of instructions uses the diagonal lines to identify the capacity of routing paths in ±

A°

directions between the sub-regions.

20. The computer readable medium of claim 19,

wherein the diagonal lines define a plurality of diagonal edges,

wherein each particular routing path intersects a particular diagonal edge,

wherein the second set of instructions derives each particular diagonal routing path'"'"'s capacity from the size of the particular diagonal edge intersected by the particular diagonal routing path.

21. The computer readable medium of claim 20,

wherein each routing path is defined with respect to a particular wiring layer and each layer has a particular pitch,

wherein the second set of instructions further derives the capacity of each particular diagonal routing path from the pitch of the particular routing path'"'"'s layer.

22. The computer readable medium of claim 21 further comprising:

d) a fourth set of instructions for hierarchically partitioning the region into smaller and smaller sub-regions;

e) a fifth set of instructions for specifying a route for each set of routable elements at each level of the hierarchy,

wherein the sub-regions at the lowest level of the hierarchy are Gcells,

wherein the second set of instructions further derives the capacity of each particular diagonal routing path at non-Gcell levels from the number of tracks of wiring at the Gcell level in the direction of the particular routing path.