Method of forming an etched metal trace with reduced RF impedance resulting from the skin effect

• US 7,098,044 B1
• Filed: 01/16/2004
• Issued: 08/29/2006
• Est. Priority Date: 08/15/2002
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Johnson, Peter, Hopper, Peter J., Hwang, Kyuwoon, Drury, Robert, Mian, Michael
• Primary Examiner(s): NGUYEN, HA T
• Application Number:
  US10/759,621
• Time in Patent Office: 956 Days
• Field of Search: 438/381, 438/704, 438/706, 438/745, 438/754, 336/200
• US Class Current: 438/3
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a layer of conductive material on a conductive region and a layer of insulation material;

etching the layer of conductive material to form a trace, the trace having a first length, a first width, a first height, a top surface and a bottom surface;

etching the trace to form a slot opening in the top surface of the trace, the slot opening having a conductive bottom surface that completely lies above the bottom surface of the trace, a second length, a second width, and a second height, the first and second lengths being substantially equal; and

forming a layer of isolation material over the trace to fill up the slot opening, the layer of isolation material contacting the conductive bottom surface of the slot opening.

2. The method of claim 1 wherein the trace is formed to have a number of loops.

3. The method of claim 2 wherein the loops lie substantially in a same plane.

4. The method of claim 1 wherein the trace is connected to a contact.

5. The method of claim 1 wherein the trace is connected to a via.

6. The method of claim 1 wherein the layer of isolation material contacts the layer of insulation material.

7. The method of claim 1 wherein the conductive material is metal.

8. A method of forming a semiconductor device, the method comprising:

forming a layer of conductive material on a conductive region and a layer of insulation material;

etching the layer of conductive material to form a trace, the trace having a length, a width, a height, a top surface, and a bottom surface;

etching the trace to form a slot opening in the top surface of the trace, the slot opening having a conductive bottom surface that completely lies above the bottom surface of the trace, and side walls that extend along the length of the trace; and

forming a layer of isolation material over the trace to fill up the slot opening, the layer of isolation material contacting the conductive bottom surface of the slot opening.

9. The method of claim 8 wherein the trace is formed to have a number of loops.

10. The method of claim 9 wherein the loops lie substantially in a same plane.

11. The method of claim 8 wherein the layer of isolation material contacts the layer of insulation material.

12. The method of claim 8 wherein the conductive material is metal.

13. The method of claim 8 wherein the slots are substantially equally spaced apart.

14. A method of forming a semiconductor device, the method comprising:

forming a layer of conductive material on a conductive region and a layer of insulation material;

etching the layer of conductive material to form a trace, the trace having a bottom surface and a substantially planar top surface;

etching the trace to form a plurality of slot openings in the top surface of the trace, each slot opening having a conductive bottom surface that completely lies above the bottom surface of the trace, a portion of each slot opening lying directly vertically over the conductive region; and

forming a layer of isolation material over the trace to fill up the slot openings, the layer of isolation material contacting the conductive bottom surface of each slot opening.

15. The method of claim 14 wherein the trace is formed to have a number of loops.

16. The method of claim 15 wherein the loops lie substantially in a same plane.

17. The method of claim 14 wherein the conductive region is a via.

18. The method of claim 14 wherein the layer of isolation material contacts the layer of insulation material.

19. The method of claim 14 wherein the conductive material is metal.

20. The method of claim 14 wherein the slots are substantially equally spaced apart.