Method of making mirror image memory cell transistor pairs featuring poly floating spacers

• US 7,098,106 B2
• Filed: 07/01/2004
• Issued: 08/29/2006
• Est. Priority Date: 07/01/2004
• Status: Expired due to Fees

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lojek, Bohumil
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Perkins, Pamela E
• Application Number:
  US10/883,159
• Publication Number:
  US 20040235305A1
• Time in Patent Office: 789 Days
• Field of Search: 438/253, 438/254, 438/257, 438/398, 438/593
• US Class Current: 438/257
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

By arranging floating spacer and gate non-volatile memory transistors in symmetric pairs, increased chip density may be attained. For each pair of such transistors, the floating gates are laterally aligned with floating spacers appearing on laterally outward edges of each floating gate. At laterally inward edges, the two transistors share a common source electrode. The transistors are independent of each other except for the shared source electrode. Tunnel oxide separated the floating spacer from the floating gate, but both the spacer and the gate are maintained at a common potential, thereby providing dual paths for charge exiting the tunnel oxide, as the charge is propelled by a programming voltage. The pairs of transistors can be aligned in columns with the direction of the columns orthogonal to the direction of the pairs, thereby forming a memory array.

Claims

1. A method of making mirror image non-volatile memory transistor pairs comprising:

building a pair of spaced apart poly floating gate structures in a isolation region of a semiconductor substrate having a surface upon which said structures are built with a gap therebetween, each structure spaced from the substrate by tunnel oxide and having opposed sidewalls on opposite sides thereof;

forming a pair of first subsurface electrodes adjacent sidewalls of the floating gate structures;

disposing a first poly spacer spaced apart by tunnel oxide to a sidewall of each floating gate structure;

after formation of the first poly spacers, forming a second subsurface electrode between the first subsurface electrodes;

forming a second poly spacer in electrically contacting relation relative to a sidewall of each floating gate structure and electrically joined to a respective first poly spacer, the second poly spacer in contact relation joining a floating gate structure and a first poly spacer;

forming a control gate in insulative relation over each floating gate structure.

2. The method of claim 1 wherein the pair of spaced apart floating gate structures are formed by dividing a single poly mesa structure with opposed lateral sides above the substrate and electrically insulated from the substrate.

3. A method of making mirror image non-volatile memory transistor pairs comprising:

providing a doped semiconductor substrate with an upper surface within an isolation region, with a gate oxide layer and a first poly layer thereon;

forming a poly mesa structure with opposed lateral sides within the isolation region above the substrate and insulated therefrom, the structure including a poly floating gate formed from the gate oxide layer and the first poly layer;

using the opposed lateral sides of the mesa structure for self aligned placement of subsurface implanted regions forming first and second spaced apart drain electrodes;

exposing portions of the implanted regions within opposed lateral sides of the mesa;

depositing tunnel oxide over exposed portions of the implanted regions and over opposed lateral sides of the mesa structure;

depositing a second poly layer over the isolation region, including over and the tunnel oxide;

etching the second poly layer leaving a pair of poly spacers on opposed lateral sides of the mesa structure;

depositing an insulative layer over the isolation region;

etching a gap in the mesa structure between the poly spacers, thereby forming two mesa substructures each with a poly floating gate, and implanting ions into the substrate below the gap thereby forming a source electrode;

depositing a third poly layer over the insulative layer;

etching the third poly layer leaving a pair of contact spacers, each contact spacer electrically joining a poly spacer and a poly floating gate of a mesa substructure; and

depositing a fourth poly layer over the mesa substructures and etching the fourth poly layer to form control gates above the floating gates of the mesa substructures.

4. The method of claim 3 further defined by forming the isolation region as a linear stripe.

5. The method of claim 3 wherein exposing of portions of the implanted regions within opposed lateral sides of the mesa is by etching at least portions of the gate oxide layer over the first and second spaced apart drain electrodes.

6. A method of making mirror image non-volatile memory transistor pairs comprising:

building a mesa structure with opposed sidewalls in an isolation region of a semiconductor substrate having a surface of upon which said structure is built, the mesa structure having a poly floating gate;

using the opposed sidewalls of the mesa structure for self aligned ion implantation of first subsurface electrodes in the substrate;

disposing first poly spacers in insulated relation relative to opposed side walls of the mesa structure;

etching a gap in the mesa structure, thereby dividing the mesa structure into two mesa substructures each with a poly floating gate, with exposed edges facing the gap;

implanting a second subsurface electrode through the gap into the substrate, the subsurface electrode being a common electrode for each of the two mesa substructures;

forming a pair of contact spacers, each contact spacer electrically joining a first poly spacer and a poly floating gate of each mesa substructure; and

forming control gates above the floating gates of the mesa substructures.

7. The method of claim 6 further defined by making the first poly spacers from a single layer of poly two prior to forming contact spacers.

8. The method of claim 6 further defined by making the poly floating gate from a single layer of poly one.

9. The method of claim 6 wherein a plane of symmetry passes through the subsurface electrode.

10. The method of claim 6 further defined by making the contact spacers from a single layer of poly three.