Semiconductor memory device using vertical-channel transistors

• US 7,098,478 B2
• Filed: 06/29/2005
• Issued: 08/29/2006
• Est. Priority Date: 01/22/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Nishida, Akio, Funayama, Kota, Sekiguchi, Tomonori, Takaura, Norikatsu, Matsuoka, Hideyuki, Takemura, Riichiro, Okuyama, Kousuke, Moniwa, Masahiro
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US11/168,872
• Publication Number:
  US 20050253143A1
• Time in Patent Office: 426 Days
• Field of Search: 257/67
• US Class Current: 257/67
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Claims

1. An SRAM device comprising:

a plurality of word lines;

a plurality of bit lines; and

a plurality of static memory cells each including a first, second, third, fourth, fifth, and sixth transistors,

wherein gates of said fifth and sixth transistors are coupled to said word lines,

wherein source and drain regions of said fifth and sixth transistors are formed inside a semiconductor substrate,

wherein channel regions, source and drain regions of said first and second transistors are formed by depositing three poly-silicon layers above a substrate surface of the semiconductor substrate,

wherein vertical sides of said three poly-silicon layers, which surfaces are vertical against said substrate surface, are completely surrounded by a gate layer and having a dioxide layer inbetween,

wherein some of said first, second, third, fourth, fifth, and sixth transistors are disposed on different surfaces from each other, and

wherein said different surfaces are electrically connected through a vertical interconnect element.

2. The SRAM device according to claim 1,

wherein said three poly-silicon layers includes a first, second, and third poly-silicon layers, and

wherein the first poly-silicon layer forms said drain regions, the second poly-silicon layer deposited above said first poly-silicon layer forms said channel regions, the third poly-silicon layer deposited above said second poly-silicon layer forms said source regions, said dioxide layer is formed around said vertical sides of a column made from etching said first, second, and third poly-silicon layers, and said gate layer is deposited around said dioxide layer.

4. The SRAM device according to claim 2,

wherein said plurality of word lines are formed in a layer between said substrate surface and said layer forming said second power line.

5. The SRAM device according to claim 2, further comprising:

a peripheral circuit including a row and column decoder,

wherein transistors forming said peripheral circuit includes veIlical transistors having currents flowing through channel regions thereof in a vertical direction which is vertical against the substrate surface.

6. The SRAM device according to claim 1,

wherein the first, second transistors are arranged in a level different from a level containing the third, fourth transistors.

7. The SRAM device according to claim 6,

wherein the transistors located in different levels are selectively connected to each other via at least one vertical interconnect.

8. The SRAM device according to claim 7,

wherein said at least one vertical interconnect cross-links with at least one of a horizontal interconnect, the first power line, and the second power line, each of which is parallel with the substrate surface.

9. The SRAM device according to claim 1,

wherein the semiconductor substrate is made of single crystal silicon.

3. A method for forming a SRAM device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each including a first, second, third, fourth, fifth, and sixth transistors, wherein gates of said fifth and sixth transistors are coupled to said word lines, wherein source and drain regions of said fifth and sixth transistors are formed inside a semiconductor substrate, comprising:

depositing three poly-silicon layers above a substrate surface of the semiconductor substrate to form channel regions, source and drain regions of said first and second transistors;

completely surrounding vertical sides of said three poly-silicon layers, which surfaces are vertical against said substrate surface, by a gate layer and providing a dioxide layer in-between;

disposing some of said first, second, third, fourth, fifth, and sixth transistors on different surfaces from each other, said different surfaces being electrically connected through a vertical interconnect element,

wherein said three poly-silicon layers includes a first, second, and third poly-silicon layers, and

wherein said first and second transistors are formed by steps of;

depositing the first poly-silicon layer which forms said drain regions,

depositing the second poly-silicon layer above said first poly-silicon layer, which forms said channel regions,

depositing the third poly-silicon layer above said second poly-silicon layer, which forms said source regions,

etching said first, second, and third poly-silicon layers to form columns, forming said dioxide layer around said vertical sides, and

depositing said gate layer around said dioxide layer.

19. The A method for forming a SRAM device according to claim 3,

wherein during the etching step, a mask covers a surface of said third poly-silicon layer which is parallel with said substrate surface, and said mask is removed before said layer forming said first power line is formed.

10. An SRAM device comprising:

a plurality of word lines;

a plurality of bit lines; and

a plurality of static memory cells each including a first, second, third, fourth, fifth, and sixth transistors,

wherein gates of said fifth and sixth transistors are coupled to said word lines,

wherein channel regions, source and drain regions of said fifth and sixth transistors are formed inside a semiconductor substrate such that currents flow via said channel regions aligning in a first direction,

wherein channel regions, source and drain regions of said first and second transistors are formed by depositing three poly-silicon layers above a substrate surface of the semiconductor substrate such that currents flow via said channel regions aligning in a second direction which crosses said first direction at an angle greater than zero degree and smaller than 90 degrees,

wherein aligning sides of said three poly-silicon layers, which surfaces are parallel with said second direction, are completely surrounded by a gate layer having a dioxide layer inbetween,

wherein some of said first, second, third, fourth, fifth, and sixth transistors are disposed on different surfaces each other, and

wherein said different surfaces are electrically connected through a vertical interconnect element.

11. The SRAM device according to claim 10,

wherein said three poly-silicon layers includes a first, second, and third poly-silicon layers, and

wherein the first poly-silicon layer forms said drain regions, the second poly-silicon layer deposited above said first poly-silicon layer forms said channel regions, the third poly-silicon layer deposited above said second poly-silicon layer forms said source regions, said dioxide layer is formed around said vertical sides of a column made from etching said first, second, and third poly-silicon layers, and said gate layer is deposited around said dioxide layer.

13. The SRAM device according to claim 11,

wherein said plurality of word lines are formed in a layer between said substrate surface and said layer forming said second power line.

14. The SRAM device according to claim 11, further comprising:

a peripheral circuit including a row and column decoder,

wherein transistors forming said peripheral circuit includes vertical transistors having currents flowing through channel regions thereof in a vertical direction which is vertical against the substrate surface.

15. The SRAM device according to claim 10,

wherein the first, second transistors are arranged in a level different from a level containing the third, fourth transistors.

16. The SRAM device according to claim 15,

wherein the transistors located in different levels are selectively connected to each other via at least one vertical interconnect.

17. The SRAM device according to claim 16,

wherein said at least one vertical interconnect cross links with at least one of a horizontal interconnect, the first power line, and the second power line, each of which is parallel with the substrate surface.

18. The SRAM device according to claim 10,

wherein the semiconductor substrate is made of single crystal silicon.

12. A method for forming a SRAM device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each including a first, second, third, fourth, fifth, and sixth transistors, wherein gates of said fifth and sixth transistors are coupled to said word lines, wherein channel regions, source and drain regions of said fifth and sixth transistors are formed inside a semiconductor substrate such that currents flow via said channel regions aligning in a first direction, comprising:

depositing three poly-silicon layers above a substrate surface of the semiconductor substrate to form channel regions, source and drain regions of said first and second transistors such that currents flow via said channel regions aligning in a second direction which crosses said first direction at an angle greater than zero degree and smaller than 90 degrees;

completely surrounding aligning sides of said three poly-silicon layers, which surfaces are parallel with said second direction, by a gate layer and providing a dioxide layer in-between;

depositing some of said first, second, third, fourth, fifth, and sixth transistors on different surfaces each other, said different surfaces being electrically connected through a vertical interconnect element,

wherein said three poly-silicon layers includes a first, second, and third poly-silicon layers, and

wherein said first and second transistors are formed by steps of;

depositing the first poly-silicon layer which forms said drain regions,

depositing the second poly-silicon layer above said first poly-silicon layer, which forms said channel regions,

depositing the third poly-silicon layer above said second poly-silicon layer, which forms said source regions,

etching said first, second, and third poly-silicon layers to form columns, forming said dioxide layer around said vertical sides, and

depositing said gate layer around said dioxide layer.

20. The A method for forming a SRAM device according to claim 12,

wherein during the etching step, a mask covers a surface of said third poly-silicon layer which is parallel with said substrate surface, and said mask is removed before said layer forming said first power line is formed.