Electro-optical device and method for manufacturing the same
First Claim
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1. An active matrix display device having a pixel portion and a driver circuit portion, said driver circuit portion including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
- a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region;
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said thin film transistors in both of the pixel portion and a part of the driver circuit portion;
a pixel electrode formed over the leveling film, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm2/V·
sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm2/V·
sec or more, and wherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, and wherein the crystalline semiconductor islands of the thin film transistors of the pixel portion and the driver circuit portion are formed by a same process simultaneously.
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Abstract
An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a plurality of source (drain) wires, and a pixel matrix comprising thin film transistors, and a second substrate facing the first substrate, wherein, among the peripheral circuits having established on the first substrate and being connected to the matrix wirings for the X direction and the Y direction, only a part of said peripheral circuits is constructed from thin film semiconductor devices fabricated by the same process utilized for an active device, and the rest of the peripheral circuits is constructed from semiconductor chips. The liquid crystal display device according to the present invention is characterized by that the peripheral circuits are not wholly fabricated into thin film transistors, but only those portions having a simple device structure, or those composed of a small number of devices, or those comprising an IC not easily available commercially, or those comprising an expensive integrated circuit, are fabricated by thin film transistors. According to the present invention, an electro-optical device is provided at an increased production yield with a reduced production cost.
344 Citations
69 Claims
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1. An active matrix display device having a pixel portion and a driver circuit portion, said driver circuit portion including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region;
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said thin film transistors in both of the pixel portion and a part of the driver circuit portion;
a pixel electrode formed over the leveling film, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm2/V·
sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm2/V·
sec or more, andwherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein the crystalline semiconductor islands of the thin film transistors of the pixel portion and the driver circuit portion are formed by a same process simultaneously. - View Dependent Claims (28, 29, 30, 31, 32, 34, 35, 38, 39, 41, 44)
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2. A semiconductor circuit having a pixel portion and a shift register, said shift register including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region;
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said thin film transistors in both of the pixel portion and the shift register; and
a pixel electrode formed over the leveling film, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm2/V·
sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm2/V·
sec or more, andwherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein the crystalline semiconductor islands of the thin film transistors of the pixel portion and the shift register are formed by a same process simultaneously. - View Dependent Claims (46)
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3. A semiconductor circuit having a pixel portion and an inverter, said inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region;
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said thin film transistors in both of the pixel portion and the inverter; and
a pixel electrode formed over the leveling film, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm2/V·
sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm2/V·
sec or more, andwherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein the crystalline semiconductor islands of the thin film transistors of the pixel portion and the inverter are formed by a same process simultaneously. - View Dependent Claims (47)
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4. A semiconductor circuit having a pixel portion and a clocked inverter, said docked inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region;
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said thin film transistors in both of the pixel portion and the clocked inverter; and
a pixel electrode formed over the leveling film, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm2/V·
sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm2/V·
sec or more, andwherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein the crystalline semiconductor islands of the thin film transistors of the pixel portion and the clocked inverter are formed by a same process simultaneously. - View Dependent Claims (48)
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5. An active matrix display device having a pixel portion and a driver circuit portion, said driver circuit portion including al least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including al least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region; and
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said thin film transistors in both of the pixel portion and a part of the driver circuit portion; and
a pixel electrode formed over the leveling film, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm2/V·
sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm2/V·
sec or more, andwherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein a laser Raman spectroscopy of the crystalline semiconductor islands of the thin film transistors of the pixel portion and the driver circuit portion exhibits a peak shifted to a lower frequency side as compared with a peak of single crystal silicon. - View Dependent Claims (49)
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6. A semiconductor circuit having a pixel portion and a shift register, said shift register including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region;
a gate electrode adjacent lo said gate insulating film;
a leveling film covering each of said thin film transistors in both of the pixel portion and in the shift register; and
a pixel electrode formed over the leveling film, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm2/V·
sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm2/V·
sec or more, andwherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein the crystalline semiconductor islands of the thin film transistors of the pixel portion and the shift register are formed by a same process simultaneously. - View Dependent Claims (50)
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7. A semiconductor circuit having a pixel portion and an inverter, said inverter including al least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region;
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said thin film transistors in both of the pixel portion and the inverter; and
a pixel electrode formed over the leveling film, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm2/V·
sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm2/V·
sec or more, andwherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein the crystalline semiconductor islands of the thin film transistors of the pixel portion and the inverter are formed by a same process simultaneously. - View Dependent Claims (51)
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8. A semiconductor circuit having a pixel portion and a clocked inverter, said clocked inverter including at least one pair of complementary p-channel and n-channel thin film transistor, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region;
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said thin firm transistors in both of the pixel portion and the docked inverter; and
a pixel electrode formed over the leveling film, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm2/V·
sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm2/V·
sec or more, wherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein the crystalline semiconductor islands of the thin film transistors of the pixel portion and the clocked inverter are formed by a same process simultaneously. - View Dependent Claims (52)
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9. An active matrix display device having a pixel portion and a driver circuit portion, said driver circuit portion including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region;
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said p-channel and n-channel thin film transistors in both of the pixel portion and a part of the driver circuit portion; and
a pixel electrode formed over the leveling film, wherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×
1019 cm−
3. - View Dependent Claims (53, 58, 59, 60)
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10. A semiconductor circuit having a pixel portion and a shift register, said shift register including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region;
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said thin film transistors in both of the pixel portion and the shift register; and
a pixel electrode formed over the leveling film, wherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×
1019 cm−
3. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 33, 36, 37, 40, 43, 45, 54, 61, 62, 63)
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11. A semiconductor circuit having a pixel portion and an inverter, said inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gale insulating film adjacent to at least said channel region;
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said thin film transistors in both of the pixel portion and the inverter; and
a pixel electrode formed over the leveling film, wherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×
109 cm−
3. - View Dependent Claims (55, 64, 65, 66, 68, 69)
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12. A semiconductor circuit having a pixel portion and a clocked inverter, said Flocked inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising:
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a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region;
a gate insulating film adjacent to at least said channel region;
a gate electrode adjacent to said gate insulating film;
a leveling film covering each of said thin film transistors in both of the pixel portion and the clocked inverter; and
a pixel electrode formed over the leveling film, wherein each of said semiconductor islands has a thickness in the range of 5000 Å
or less, andwherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×
1019 cm−
3. - View Dependent Claims (56, 67)
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21. An active matrix display device including a pixel portion and a driver circuit portion comprising:
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a plurality of pixel electrodes formed on an insulating surface;
a first plurality of thin him transistors being formed in the pixel portion on said insulating surface and being connected to said pixel electrodes;
a second plurality of thin film transistors being formed in the driver circuit portion on said insulating surface, said second plurality of thin film transistors including at least one pair of complementary p-channel and n-channel thin film transistors; and
a leveling film covering both of the first and second plurality of thin film transistors in the pixel portion and a part of the driver circuit portion, wherein said pixel electrodes are formed over the leveling film, wherein said second plurality of thin film transistors in said driver circuit include channel semiconductor layers having at east one of an electron mobility 15 cm2/V·
sec or more and a hole mobility of 10 cm2/V·
sec or more, andwherein each of said channel semiconductor layers has a thickness of 5000 Å
or less. - View Dependent Claims (22, 23, 24, 25, 26, 27, 42, 57)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsYamazaki, Shunpei
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Primary Examiner(s)JACKSON JR, JEROME
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Application NumberUS09/583,087Time in Patent Office2,401 DaysField of Search257/338, 257/350, 257/369, 257/72, 349/41US Class Current257/72CPC Class CodesH01L 27/1214 comprising a plurality of T...
