Semiconductor device and method for fabricating the same

• US 7,098,506 B2
• Filed: 01/31/2005
• Issued: 08/29/2006
• Est. Priority Date: 06/28/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Inagawa, Hiroshi, Machida, Nobuo, Ooishi, Kentaro
• Primary Examiner(s): TSAI, HUI JEY
• Application Number:
  US11/045,148
• Publication Number:
  US 20050127437A1
• Time in Patent Office: 575 Days
• Field of Search: 257328-345
• US Class Current: 257/330
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Claims

1. A semiconductor device including a trench-gate MISFET, comprising:

a semiconductor body having a first conduction type;

a drain region of the trench-gate MISFET having the first conduction type, formed over the semiconductor body;

a base region of the trench gate MISFET having a second conduction type which is opposite to the first conduction type, formed over the drain region,

a source region of the trench-gate MISFET having the first conduction type, formed over the base region;

a trench extending from an upper surface of the source region to the drain region;

a gate insulating film of the trench-gate MISFET formed on an inner wall of the trench;

a gate electrode of the trench-gate MISFET formed on the gate insulating film;

an insulating film formed over the source region and gate electrode,

a contact hole formed in the insulating film and exposing the base region and an upper surface and a side surface of the source region; and

a source wiring formed in the contact hole and electrically connected with the source region and base region;

wherein the contact hole is comprised of a lower portion and an upper portion;

the lower portion of the contact hole penetrates the source region and reaches the base region;

the lower portion of the contact hole reaches a side surface of the source region; and

the upper portion of the contact hole reaches the upper surface of the source region.

2. The semiconductor device according to claim 1, wherein a width of the upper portion of the contact hole is larger than that of the lower portion of the contact hole.

3. The semiconductor device according to the claim 1, wherein the first and second conduction types are an n type and a p type, respectively.

4. The semiconductor device according to claim 1, wherein a channel is formed in the base region.

5. The semiconductor device according to claim 1, wherein the semiconductor device has a plurality of the trench gate MISFETs, the source regions, base regions, and drain regions of the plurality of the trench-gate MISFETs are electrically connected respectively, and the plurality of the trench-gate MISFETs comprise a power MISFET.

6. The semiconductor device according to claim 1, wherein a drain electrode is formed over a back surface of the semiconductor body;

and the drain electrode and the drain region are electrically connected.

7. The semiconductor device according to claim 1, wherein a contact layer is formed in the base region;

the contact layer and the base region have a same conduction type;

an impurity concentration of the contact layer is greater than that of the base region; and

the lower portion of the contact hole reaches the contact layer.

8. The semiconductor device according to claim 1, wherein the source wiring reaches the upper and side surfaces of the source region.