Embedded redistribution interposer for footprint compatible chip package conversion
First Claim
1. An embedded redistribution interposer for providing footprint compatible chip package migration in which a die designed for mounting into a chip package with footprint compatibility with a first type of silicon platform is originally implemented using the first type of silicon platform and is subsequently redesigned for a second type of silicon platform, resulting in a redesigned die being a different size than the original die and no longer compatible for mounting in the chip package, the embedded redistribution interposer comprising:
- an interposer substrate having top and bottom sides, wherein the redesigned die for the second type of silicon platform is mounted on the top side of the interposer substrate, and the bottom side of the interposer substrate is mounted to a substrate of the chip package with footprint compatibility with the first type of silicon platform;
a plurality of bond pads;
a first set of electrical connections coupled between the redesigned die and the plurality of bond pads to connect the redesigned die to the redistribution interposer; and
a second set of electrical connections coupled between the plurality of bond pads and the chin package substrate to connect the redistribution interposer to the chip package, wherein signals from the redesigned die are redistributed from the redesigned die such that die fan-out is increased without violating assembly rules, thereby eliminating the need to redesign the chip package to accommodate the redesigned die.
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Abstract
An embedded redistribution interposer is disclosed for providing footprint compatible chip package migration in which a die designed to be mounted into chip package is originally implemented using a first type of silicon platform and is subsequently redesigned for a second type of silicon platform, resulting in a redesigned die being a different size than the original die and no longer compatible for mounting in the chip package. According to the present invention, the embedded redistribution interposer includes a substrate having a plurality of bond pads on a top side thereof, wherein the redesigned die is mounted to the top of the interposer substrate, and the bottom of the interposer substrate is mounted to the substrate of the chip package. The redesigned die is connected to the redistribution interposer via a first set of electrical connections coupled between the die and the interposer bond pads. The redistribution interposer is then connected to the package via a second set of electrical connections coupled between the interposer bond pads and a package substrate, wherein signals from the die are redistributed in a manner that increases die fan-out without violating assembly rules, thereby eliminating the need to redesign the chip package to accommodate the redesigned die, resulting in a footprint compatible package.
32 Citations
19 Claims
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1. An embedded redistribution interposer for providing footprint compatible chip package migration in which a die designed for mounting into a chip package with footprint compatibility with a first type of silicon platform is originally implemented using the first type of silicon platform and is subsequently redesigned for a second type of silicon platform, resulting in a redesigned die being a different size than the original die and no longer compatible for mounting in the chip package, the embedded redistribution interposer comprising:
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an interposer substrate having top and bottom sides, wherein the redesigned die for the second type of silicon platform is mounted on the top side of the interposer substrate, and the bottom side of the interposer substrate is mounted to a substrate of the chip package with footprint compatibility with the first type of silicon platform; a plurality of bond pads; a first set of electrical connections coupled between the redesigned die and the plurality of bond pads to connect the redesigned die to the redistribution interposer; and a second set of electrical connections coupled between the plurality of bond pads and the chin package substrate to connect the redistribution interposer to the chip package, wherein signals from the redesigned die are redistributed from the redesigned die such that die fan-out is increased without violating assembly rules, thereby eliminating the need to redesign the chip package to accommodate the redesigned die. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A chip package, comprising:
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a chip package substrate comprising bond pads and a pin-out connecting the chip package substrate to a board, wherein the chip package substrate is footprint compatible with a first type of silicon platform; a redesigned die that was originally designed for the first type of silicon platform for mounting in the chip package substrate and was subsequently migrated to a second silicon platform, resulting in a smaller form factor; a redistribution interposer embedded between the chip package substrate and the redesigned die, the redistribution interposer comprising; a plurality of interposer bond pads; a first plurality of wire bonds coupled between the redesigned die and the plurality of interposer bond pads; a second plurality of wire bonds coupled between the interposer bond pads and the bond pads on the chip package substrate, thereby redistributing signals from the redesigned die and increasing radial fan-out, thereby maintaining footprint compatibility with the chip package substrate and eliminating need to redesign the chip package or the board to accommodate the designed die. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A method for providing die migration from a first type of silicon platform to a second type of silicon platform while maintaining chip package footprint compatibility, comprising:
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(a) redesigning a die originally designed for mounting in a chip package substrate with footprint compatibility with the type of silicon platform from the first type silicon platform to the second type of silicon platform, resulting in a redesigned die having a smaller form factor than the original die, wherein the chip package substrate comprises a substrate having a plurality of bond pads thereon; (b) embedding a redistribution interposer between the chip package substrate and the redesigned die; (c) providing the redistribution interposer with a plurality of bond pads; (d) coupling a first plurality of wire bonds between the redesigned die and the interposer bond pads; and (e) coupling a second plurality of wire bonds between the interposer bond pads and the bond pads on the chip package substrate, thereby redistributing signals from the redesigned die and increasing radial fan-out, thereby maintaining footprint compatibility with the chip package substrate and eliminating need to redesign the chip package to accommodate the redesigned die.
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Specification