Depth determining system

• US 7,098,669 B2
• Filed: 09/20/2004
• Issued: 08/29/2006
• Est. Priority Date: 10/01/2003
• Status: Active Grant

• Current Assignee: Flowline, Inc.
• Original Assignee: Flowline, Inc.
• Inventors: Carter, Larry
• Primary Examiner(s): Lee, Diane
• Assistant Examiner(s): Dole, Timothy J.
• Application Number:
  US10/945,419
• Publication Number:
  US 20050072227A1
• Time in Patent Office: 708 Days
• Field of Search: 324/605, 324/607, 324/644
• US Class Current: 324/605
• CPC Class Codes: G01F 23/2962 Measuring transit time of reflected waves
• CPC Class Codes: G01N 2291/02836 Flow rate, liquid level
• CPC Class Codes: G01N 29/024 by measuring propagation velocity or propagation time of acoustic waves
• CPC Class Codes: G01N 29/40 by amplitude filtering, e.g. by applying a threshold or by gain control
• CPC Class Codes: G01S 7/5273 using digital techniques

Abstract

A system for determining the depth of a fluid in a storage tank. The depth of the fluid is determined after the detection of a pulsed wave that is reflected from the top surface of the fluid. The system includes a transducer, an analog-to-digital converter, and a filter. The transducer is configured to sense the reflected pulsed wave and to generate an analog input signal that corresponds to the reflected pulsed wave. The analog-to-digital converter is coupled to the transducer, and configured to convert the analog input signal into a digital input signal. The filter is coupled to the analog-to-digital converter. The filter includes a finite impulse response filter that is configured to receive the digital input signal and to generate a digital output signal.

Claims

1. A system for determining the depth of a fluid in a storage tank, wherein the depth of the fluid is determined after the detection of a pulsed wave that is reflected from the top surface of the fluid, the system comprising:

a. a transducer configured to measure the reflected pulsed wave and to generate an analog input signal that corresponds to the reflected pulsed wave;

b. an analog-to-digital converter that is coupled to the transducer, and configured to convert the analog input signal into a digital input signal; and

c. a filter that is coupled to the analog-to-digital converter, wherein the filter includes a finite impulse response filter that is configured to receive the digital input signal and to generate a digital output signal, the finite impulse response filter including;

i. a two-stage shift register,

ii. a first subtractor that is coupled to the two-stage shift register,

iii. an n/2-stage shift register that is coupled to the first subtractor, where n is an even integer greater than or equal to four,

iv. a second subtractor that is coupled to both the first subtractor and the n/2-stage shift register,

v. an adder that is coupled to the second subtractor, and

vi. a storage register that is coupled to the adder.

2. The system according to claim 1, further comprising:

a. a threshold and peak detector coupled to the filter, where the threshold and peak detector is configured to compare an amplitude of the digital output signal from the finite impulse response filter to a threshold value, and to create a list of peaks, including an amplitude value and a time of each peak that exceeds the threshold value, in real time;

b. a control circuit that is coupled to bath the filter and the threshold and peak detector, where the control circuit is configured to receive the list of peaks from the threshold and peak detector; and

c. a storage device coupled to the control circuit that is configured to store the list of peaks received by the control circuit.

3. The system according to claim 2, further comprising:

a. a signal generator that is coupled between the control circuit and the transducer, and that is configured to generate a generator signal that is used to stimulate the transducer to induce the pulsed wave; and

b. a driver coupled between the signal generator and the transducer that is configured to amplify the generator signal before the generator signal is coupled into to the transducer.

4. The system according to claim 3, wherein the filter includes a matched filter that is configured to compare the analog input signal to the generator signal.

5. The system according to claim 2, wherein the control circuit calculates a value of the depth of the fluid in the storage tank based on the list of peaks, and the control circuit generates a digital pulse-width-modulated signal that varies in modulation based on the depth of the fluid in the storage tank, the system further comprising:

a. a digital-to-analog converter that is coupled to the control circuit and configured to convert the digital pulse-width-modulated signal into an analog pulse-width-modulated signal;

b. a level-signaling circuit that is coupled to the digital-to-analog converter, and is configured to convert the analog pulse-width-modulated signal into a level-signaling output signal correlates to the depth of the fluid in the storage tank; and

c. a temperature sensor that is coupled to the control circuit and that is configured to provide the control circuit with a temperature value for the fluid in the storage tank, wherein the control circuit adjusts the calculated value of the depth of the fluid in the storage tank based on the temperature value for the fluid in the storage tank.

6. The system according to claim 1, further comprising an amplifier coupled between the transducer and the analog-to-digital converter and configured to amplify the analog input signal.

7. The system according to claim 1, wherein:

a. the filter includes a complex filter having a first finite impulse response filter and a second finite impulse response filter that sample the digital input signal at twice the frequency of the pulsed wave; and

b. the sampled digital input signal filtered by the first finite impulse response filter is 90°

out of phase with respect to the sampled digital input signal filtered by the second finite impulse response filter.

8. The system according to claim 7, wherein the filter calculates a square root of a sum of squares value of a signal output from the first finite impulse response filter and a signal output from the second finite impulse response filter.

9. The system according to claim 7, wherein the filter calculates an approximate value of a square root of a sum of squares value by adding the larger of an absolute value of a signal output from the first finite impulse response filter and an absolute value of a signal output from the second finite impulse response filter to 3/8 times the smaller of the absolute value of the signal output from the first finite impulse response filter and the absolute value of the signal output from the second finite impulse response filter.

10. The system according to claim 9, wherein the approximate value of the square root of the sum of squares value is calculated by:

a. shifting the n/2-stage shift register to the right twice for the first or second finite impulse response filter that has the smaller absolute value of output signal;

b. adding an output of the twice right-shifted, n/2-stage shift register to the output of the first or second finite impulse response filter that has the larger absolute value, resulting in a first added value;

c. shifting the n/2-stage shift register having the smaller absolute value of output signal once more to the right; and

d. adding the output of the thrice right-shifted, n/2-stage shift register to the first added value.

11. The system according to claim 7, wherein the filter is configured to determine the phase difference between the digital input signal and coefficients that define the filter.

12. The system according to claim 1, wherein:

a. the first subtractor has two input terminals and an output terminal, and each of the first subtractor'"'"'s input terminals is coupled to one of the stages of the two-stage shift register;

b. the n/2-stage shift register has an input terminal that is coupled to the output terminal of the first subtractor;

c. the second subtractor has a first input terminal that is coupled to the output terminal of the first subtractor, a second input terminal that is coupled to the n/2th stage of the n/2-stage shift register, and an output terminal;

d. the adder has a first input terminal that is coupled to the second subtractor'"'"'s output terminal, a second input terminal, and an output terminal; and

e. the storage register has an input terminal that is coupled to the adder'"'"'s output terminal, and an output terminal that is coupled to the adder'"'"'s second input terminal.

13. The system according to claim 1, further comprising:

a. a threshold and peak detector coupled to the filter, where the threshold and peak detector is configured to compare an amplitude of the digital output signal from the finite impulse response filter to a threshold value, and to create a list of peaks, including an amplitude value and a time of each peak that exceeds the threshold value, in real time;

b. a control circuit that is coupled to both the filter and the threshold and peak detector, where the control circuit is configured to receive the list of peaks from the threshold and peak detector, the control circuit calculates a value of the depth of die fluid in the storage tank based on the list of peaks, and the control circuit generates a digital pulse-width-modulated signal that varies in modulation based on the depth of the fluid in the storage tank;

c. a storage device coupled to the control circuit that is configured to store the list of peaks received by the control circuit;

d. a digital-to-analog converter that is coupled to the control circuit and configured to convert the digital pulse-width-modulated signal into an analog pulse-width-modulated signal; and

e. a level-signaling circuit that is coupled to the digital-to-analog converter, and that is configured to convert the analog pulse-width-modulated signal into a level-signaling output signal that correlates to the depth of the fluid in the storage tank.

14. The system according to claim 13, wherein the threshold and peak detector recalculates the threshold value based on the value of the amplitude values of the digital output signal.

15. The system according to claim 13, wherein:

a. the filter includes a complex fitter having a first finite impulse response filter and a second finite impulse response filter that sample the digital input signal at twice the frequency of the pulsed wave; and

b. the sampled digital input signal filtered by the first finite impulse response filter is 90°

out of phase with respect to the sampled digital input signal filtered by the second finite impulse response filter.

16. The system according to claim 13, wherein the filter calculates a square root of a sum of squares value of a signal output from the first finite impulse response filter and a signal output from the second finite impulse response filter.

17. The system according to claim 13, wherein the filter calculates an approximate value of a square root of a sum of squares value by adding the larger of an absolute value of a signal output from the first finite impulse response filter and an absolute value of a signal output from the second finite impulse response filter to 3/8 times the smaller of the absolute value of the signal output from the first finite impulse response filter and the absolute value of the signal output from the second finite impulse response filter.

18. The system according to claim 13, wherein the filter is configured to determine the phase difference between the digital input signal that corresponds to the reflected pulsed wave and the sampled digital signal.

19. The system according to claim 1, wherein the finite impulse response filter is configured to calculate a digital output signal at time t₀, Output (t₀), based on (1) the digital input signal at time t₀, Input (t₀);

(2) the digital output signal at time t₁, Output (t₁); and

(3) a data value in the final stage of the n/2-stage shift register at time t₀, X<sub>n−

2</sub> (t₀)−

X<sub>n−

1</sub> (t₀), where t₀ is the time at the current clock cycle and t₁ was the time at the previous clock cycle, and Output (t₀) is calculated based on the following equation;

Output (t₀)−

Input (t₀)−

Input (t₁)−

X<sub>n−

2</sub> (t₀)+X<sub>n−

1</sub> (t₀)+Output (t₁).

20. A system for determining the depth of a fluid in a storage tank, wherein the depth of the fluid is determined after the detection of a pulsed wave that is reflected from the top surface of the fluid, the system comprising:

a. a transducer configured to measure the reflected pulsed wave and to generate an analog input signal that corresponds to the reflected pulsed wave;

b. an analog-to-digital converter configured to convert the analog input signal into a digital input signal; and

c. a finite impulse response filter configured to receive the digital input signal and to generate a digital output signal, wherein the filter includes a shift register that stores a succession of values based on the digital input signal, and wherein the filter generates each successive value of the digital output signal based on (1) the previous value of the digital output signal, (2) the current value of the digital input signal, and (3) a value stored in the shift register.

21. The system according to claim 20, further comprising:

a. a threshold and peak detector coupled to the filter, where the threshold and peak detector is configured to compare an amplitude of the digital output signal from the impulse response filter to a threshold value, and to create a list a peaks, including an amplitude value and a time of each peak that exceeds the threshold value, in real time;

b. a control circuit that is coupled to both the filter and the threshold and peak detector, where the control circuit is configured to receive the list of peaks from the threshold and peak detector, the control circuit calculates a value of the depth of the fluid in the storage tank based on the list of peaks, and the control circuit generates a digital pulse-width-modulated signal that varies in modulation based on the depth of the fluid in the storage tank;

c. a storage device coupled to the control circuit that is configured to store the list of peaks received by the control circuit;

d. a digital-to-analog converter that is coupled to the control circuit and configured to convert the digital pulse-width-modulated signal into an analog pulse-width-modulated signal; and

e. a level-signaling circuit that is coupled to the digital-to-analog converter, and is configured to convert the analog pulse-width-modulated signal into a level-signaling output signal that correlates to the depth of the fluid in the storage tank.

22. The system according to claim 21, wherein the threshold and peak detector recalculates the threshold value based on the value of the amplitude values of the digital output signal.

23. The system according to claim 20, wherein:

a. the filter includes a complex filter having a first finite impulse response filter and a second finite impulse response filter that sample the digital input signal at twice the frequency of the pulsed wave; and

b. the sampled digital input signal filtered by the first finite impulse response filter is 90°

out of phase with respect to the sampled digital input signal filtered by the second finite impulse response filter.

24. The system according to claim 23, wherein the filter calculates a square root of a sum of squares value of a signal output from the first finite impulse response filter and a signal output from the second finite impulse response filter.

25. The system according to claim 23, wherein the filter calculates an approximate value of a square root of a sum of squares value by adding the larger of an absolute value of a signal output from the first finite impulse response filter and an absolute value of a signal output from the second finite impulse response filter to ⅜

times the smaller of the absolute value of the signal output from the first finite impulse response filter and the absolute value of the signal output from the second finite impulse response filter.

26. The system according to claim 23, wherein the filter is configured to determine the phase difference between the digital input signal and coefficients that define the filter.

27. A system as defined in claim 20, wherein:

a. the shift register of the finite impulse response filter has n/2 stages, where n is an even integer greater than or equal to four; and

b. the finite impulse response filter further comprises;

i. a two-stage shift register,

ii. a first subtractor coupled to the two-stage shift register and to the n/2-stage shift register,

iii. a second subtractor coupled both to the first subtractor and to the n/2-stage shift register,

iv. an adder coupled to the second subtractor, and

v. a storage register coupled to the adder.

28. A system as defined in claim 27, wherein:

a. the two-stage shift register is configured to store the current value of the digital input signal, Input (t₀), and the previous value of the digital input signal, Input (t₁);

b. the first subtractor is configured to determine the difference between Input (t₀) and Input (t₁), to produce a difference value X₀−

X₁;

c. the n/2-stage shift register is configured to store previous n/2 successive difference values produced by the first subtractor;

d. the second subtractor is configured to determine the difference between the current difference value X₀−

X₁ and the difference value stored in the final stage of the n/2-stage shift register, X<sub>n−

2</sub>−

X<sub>n−

1</sub>, to produce an output value;

e. the adder is configured to determine the sum of the current output value produced by the second subtractor and the previous value of the digital output signal, Output (t₁), to produce the current value of the digital output signal, Output (t₀); and

f. the storage register is configured to store the previous value of the digital output signal, Output (t₁) and provide it to the adder.

29. A system as defined in claim 20, wherein the finite impulse response filter is configured to calculate a digital output signal at time t₀, Output (t₀), based on (1) the difference between the digital input signal at time t₀, Input (t₀), and the digital input signal at time t₁, Input (t₁);

(2) a digital output signal at time t₁, Output (t₁); and

(3) the difference between the digital input signal at time t<sub>n−

2</sub>, Input (t<sub>n−

2</sub>), and the digital input signal at time t<sub>n−

1</sub>, Input (t<sub>n−

1</sub>), which is stored in the final stage of the n/2-stage shift register at time t₀.