Structured integrated circuit device

• US 7,098,691 B2
• Filed: 07/27/2004
• Issued: 08/29/2006
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi, Apostol, Adrian, Zeman, Richard, Iacobut, Romeo, Wurman, Ze'ev, Avram, Petrica, Leventhal, Adam
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/899,020
• Publication Number:
  US 20060022705A1
• Time in Patent Office: 763 Days
• Field of Search: 326 37- 41, 326 46- 47, 326/101
• US Class Current: 326/47
• CPC Class Codes: G01R 31/3172 Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Claims

1. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells, each logic cell comprising at least one look-up tablet;

said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer;

a multiplicity of device customized I/O cells, wherein said customized I/O cells are customized by said custom via layer;

a customizable clock distribution structure, wherein said customizable clock distribution structure is customized by said custom via layer; and

a customizable trimmer cell to fine tune said clock distribution structure, wherein said customizable trimmer cell is customized by said custom via layer.

2. A semiconductor device according to claim 1, also comprising a configurable RAM block, and wherein said RAM block configuration is customized by said custom via layer.

3. A semiconductor device according to claim 1, also comprising a configurable ROM block, and wherein said ROM block content is customized by said custom via layer.

4. A semiconductor device according to claim 1, wherein said custom via layer is produced by wafer exposure directly from electronic data of said custom via layer.

5. A semiconductor device according to claim 1, wherein each said logic cell further includes a multiplexer.

6. A semiconductor device according to claim 1, wherein each said logic cell further includes a NAND gate.

7. A semiconductor device according to claim 1, wherein each said logic cell further includes a multiplicity of buffers.

8. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, each logic cell including at least one flip-flop;

at least one metal connection layer overlying the multiplicity of identical logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer;

a multiplicity of device customized I/O cells, wherein said customized I/O cells are customized by said custom via layer; and

a configurable RAM block, wherein said RAM block configuration is customized by said custom via layer;

wherein said configurable RAM port includes via options for wired or logic multiplexing output of multiple RAMs.

9. A semiconductor device according to claim 8, also comprising a built-in microprocessor, wherein said microprocessor has the ability to access said RAM block by a separate read/write port from a configurable RAM port.

10. A semiconductor device according to claim 8, also comprising a configurable ROM block, and wherein content of said configurable ROM block is customized by said custom via layer.

11. A semiconductor device according to claim 8, wherein said custom via layer is produced by wafer exposure directly from electronic data of said custom via layer.

12. A semiconductor device according to claim 8, wherein each said logic cell further includes a multiplexer.

13. A semiconductor device according to claim 8, wherein each said logic cell further includes a NAND gate.

14. A semiconductor device according to claim 8, wherein each said logic cell further includes a multiplicity of buffers.

15. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, each logic cell including at least one flip-flop;

at least one metal connection layer overlying the multiplicity of identical logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer;

a multiplicity of device customized I/O cells, wherein said customized I/O cells are customized by said custom via layer;

a customizable clock distribution structure, wherein said customizable clock distribution structure is customized by said custom via layer; and

a customizable trimmer cell to fine tune said clock distribution structure, wherein said customizable trimmer cell is customized by said custom via layer.

16. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells, each logic cell comprising at least one look-up table, said logic array also comprising metal connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof; and

a built-in microprocessor,

wherein said microprocessor has the ability to perform testing of said logic array.

17. A semiconductor device according to claim 16, and also comprising a configurable ROM block.

18. A semiconductor device according to claim 16,

wherein said microprocessor has the ability to load or to read content of said look-up table.

19. A semiconductor device according to claim 16, wherein said custom via layer is produced by wafer exposure directly from electronic data of said custom via layer.

20. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells, each logic cell comprising at least one look-up table, said logic array also comprising metal connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof; and

a built-in microprocessor; and

a configurable RAM block, wherein said microprocessor has the ability to perform testing of said RAM block.

21. A semiconductor device according to claim 20, and also comprising a configurable ROM block.

22. A semiconductor device according to claim 20,

wherein said microprocessor has the ability to load or to read content of said look-up table.

23. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, each logic cell including at least one flip-flop;

at least one metal connection layer overlying the multiplicity of identical logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof; and

a built-in microprocessor,

wherein said microprocessor has the ability to perform testing of said logic array.

24. A semiconductor device according to claim 23, and also comprising a configurable ROM block.

25. A semiconductor device according to claim 23, wherein said microprocessor has the ability to load or to read content of a look-up table included in said semiconductor device.

26. A semiconductor device according to claim 23, wherein said custom via layer is produced by wafer exposure directly from electronic data of said custom via layer.

27. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, each logic cell including at least one flip-flop;

at least one metal connection layer overlying the multiplicity of identical logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof;

a built-in microprocessor; and

a configurable RAM block, and

wherein said microprocessor has the ability to perform testing of said RAM block.

28. A semiconductor device according to claim 27, and also comprising a configurable ROM block.

29. A semiconductor device according to claim 27, wherein said microprocessor has the ability to load or to read content of a look-up table included in said semiconductor device.

30. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells, each logic cell comprising at least one look-up table;

said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer;

a multiplicity of device customized I/O cells, wherein said customized I/O cells are customized by said custom via layer;

wherein said I/O cells comprise a dedicated row of pads, and wherein said dedicated row of pads is dedicated to provide one or more power connections for said customized I/O cell.

31. A semiconductor device according to claim 30, and wherein said dedicated row of pads provides power connection to said logic array.

32. A semiconductor device according to claim 30, and wherein said dedicated row of pads is an outer row of pads.

33. A semiconductor device according to claim 30, wherein the I/O cells comprise at least three rows of pads, and wherein said dedicated row of pads is a third row of pads.

34. A semiconductor device according to claim 30, and wherein said dedicated row of pads has no connection to an I/O cell input or output signal.

35. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, each logic cell including at least one flip-flop;

at least one metal connection layer overlying the multiplicity of identical logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer;

a multiplicity of device customized I/O cells, wherein said customized I/O cells are customized by said custom via layer;

a customizable clock distribution structure, wherein said customizable clock distribution structure is customized by said custom via layer, and wherein said customizable clock distribution structure contains constant loading at each stage of the distribution to maintain a pre-characterized delay regardless of customization by said custom via layer.