Output voltage correction circuit for multiplexed multi-phase hysteretic voltage regulator
First Claim
1. A circuit for voltage regulation, comprising:
- a timing logic circuit that is arranged to provide a plurality of timing control voltages in response to a first digital voltage and a second digital voltage, wherein the first digital voltage and the second digital voltage are associated with a first phase and a second phase of multiplexing;
a sample-and-hold circuit that is arranged to track a first multiplexed voltage and a second multiplexed voltage based on the plurality of timing control signals, and is further arranged to provide a correction voltage in response to the tracked multiplexed voltages, wherein the first multiplexed voltage and the second multiplexed voltage are phase-shifted; and
a multiplexed hysteretic control circuit that is arranged to provide a regulated output voltage in response to an input voltage and the correction voltage such that an offset of the output voltage that is caused by the multiplexing is corrected.
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Accused Products
Abstract
A method and circuit for compensating offset error caused by multiplexing in hysteretic control loops. An offset voltage, caused by one phase descending without being hysteretically controlled while another phase is being controlled, is determined by a sample-and-hold circuit that is arranged to track a low limit voltage Vlo and a lowest voltage Vvalley. The offset voltage is one half of a difference between Vlo and Vvalley. A timing and control circuit provides timing control voltages to the sample-and-hold circuit based on input signals associated with phase 1 and phase 2. The sample-and-hold circuit provides Vlo and Vvalley to a differential amplifier that is arranged to provide the offset voltage to a hysteretic controller circuit. In one embodiment, the offset voltage is added to a reference voltage for corrected output voltage. In another embodiment, the offset voltage is added to the output voltage.
61 Citations
20 Claims
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1. A circuit for voltage regulation, comprising:
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a timing logic circuit that is arranged to provide a plurality of timing control voltages in response to a first digital voltage and a second digital voltage, wherein the first digital voltage and the second digital voltage are associated with a first phase and a second phase of multiplexing; a sample-and-hold circuit that is arranged to track a first multiplexed voltage and a second multiplexed voltage based on the plurality of timing control signals, and is further arranged to provide a correction voltage in response to the tracked multiplexed voltages, wherein the first multiplexed voltage and the second multiplexed voltage are phase-shifted; and a multiplexed hysteretic control circuit that is arranged to provide a regulated output voltage in response to an input voltage and the correction voltage such that an offset of the output voltage that is caused by the multiplexing is corrected. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for correcting an offset caused by multiplexing in a hysteretic regulation circuit, the method comprising:
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sampling a first multiplexed voltage based on a first timing control voltage and a second timing control voltage; sampling a second multiplexed voltage based on a first timing control voltage and a second timing control voltage in reverse order; determining a low hysteretic limit voltage based on sampling the first multiplexed voltage and the second multiplexed voltage; sampling the first multiplexed voltage based on a plurality of other timing control voltages; sampling the second multiplexed voltage based on a plurality of the other timing control voltages; determining a lowest voltage based on sampling the first multiplexed voltage and the second multiplexed voltage based on the other timing control voltages; and determining a correction voltage based on the low hysteretic limit voltage and the lowest voltage. - View Dependent Claims (17, 18, 19)
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20. A multiplexed hysteretic voltage regulation circuit, comprising:
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a sample-and-hold circuit that is arranged to track a first phase and a second phase of a hysteretic voltage and to provide a correction voltage in response to a plurality of timing control voltages that are associated with the first phase and the second phase; and a hysteretic control circuit that is arranged to provide a regulated output voltage based, in part, of the correction voltage, wherein the correction voltage is added to at least one of a reference voltage and the output voltage such that a DC offset of the output voltage that is caused by the multiplexing is corrected.
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Specification