Output voltage correction circuit for multiplexed multi-phase hysteretic voltage regulator

• US 7,098,728 B1
• Filed: 08/11/2004
• Issued: 08/29/2006
• Est. Priority Date: 08/11/2004
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Mei, Tawen, Song, Chunping
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US10/915,816
• Time in Patent Office: 748 Days
• Field of Search: 327/538
• US Class Current: 327/538
• CPC Class Codes: H02M 3/1563 without using an external clock H02M3/158 takes precedence
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A method and circuit for compensating offset error caused by multiplexing in hysteretic control loops. An offset voltage, caused by one phase descending without being hysteretically controlled while another phase is being controlled, is determined by a sample-and-hold circuit that is arranged to track a low limit voltage V_lo and a lowest voltage V_valley. The offset voltage is one half of a difference between V_lo and V_valley. A timing and control circuit provides timing control voltages to the sample-and-hold circuit based on input signals associated with phase 1 and phase 2. The sample-and-hold circuit provides V_lo and V_valley to a differential amplifier that is arranged to provide the offset voltage to a hysteretic controller circuit. In one embodiment, the offset voltage is added to a reference voltage for corrected output voltage. In another embodiment, the offset voltage is added to the output voltage.

Claims

1. A circuit for voltage regulation, comprising:

a timing logic circuit that is arranged to provide a plurality of timing control voltages in response to a first digital voltage and a second digital voltage, wherein the first digital voltage and the second digital voltage are associated with a first phase and a second phase of multiplexing;

a sample-and-hold circuit that is arranged to track a first multiplexed voltage and a second multiplexed voltage based on the plurality of timing control signals, and is further arranged to provide a correction voltage in response to the tracked multiplexed voltages, wherein the first multiplexed voltage and the second multiplexed voltage are phase-shifted; and

a multiplexed hysteretic control circuit that is arranged to provide a regulated output voltage in response to an input voltage and the correction voltage such that an offset of the output voltage that is caused by the multiplexing is corrected.

2. The circuit of claim 1, wherein the timing logic circuit comprises:

a first timing control module that is arranged to provide a first timing control voltage phi_a and a second timing control voltage phi_b in response to the first digital voltage phi1 and the second digital voltage phi2, wherein phi_a and phi_b are employed in controlling a sample-timing and a hold-timing of a first sample-and-hold module;

a second timing control module that is arranged to provide a third timing control voltage t_a, and a fourth timing control voltage t_c in response to phi1, phi_a, and phi_b, wherein another sample-timing and another hold-timing of a second sample-and-hold module is controlled based, in part, on t_a and t_c; and

a third timing control module that is arranged to provide a fifth timing control voltage t_b, and a sixth timing control voltage t_d in response to phi2, phi_a, and phi_b, wherein t_a, t_b, t_c, and t_d are employed to control a further sample-timing and a further hold-timing of a third sample-and-hold module.

3. The circuit of claim 2, wherein:

the first timing control module comprises;

a first flip flop that is arranged to receive phi1, and to control two cascaded transistors that are arranged to provide phi_b; and

a second flip flop that is arranged to receive phi2, and to control two other cascaded transistors that are arranged to provide phi_a;

the second timing control module comprises;

a first AND operator that is arranged to receive phi1 and phi_a, and to provide an AND'"'"'ed output voltage to a third flip flop that is arranged to control two cascaded transistors that are arranged to provide t_a; and

a second AND operator that is arranged to receive phi1 and phi_b, and to provide an AND'"'"'ed output voltage to a fourth flip flop that is arranged to control two other cascaded transistors that are arranged to provide t_c; and

the third timing control module comprises;

a third AND operator that is arranged to receive phi2 and phi_a, and to provide an AND'"'"'ed output voltage to a fifth flip flop that is arranged to control two cascaded transistors that are arranged to provide t_b; and

a fourth AND operator that is arranged to receive phi2 and phi_b, and to provide an AND'"'"'ed output voltage to a sixth flip flop that is arranged to control two other cascaded transistors that are arranged to provide t_d.

4. The circuit of claim 2, wherein the sample-and-hold circuit comprises:

the first sample-and-hold module arranged to sample the first multiplexed voltage and the second multiplexed voltage based on phi_a and phi_b, and to provide a low limit voltage V_lo for the hysteretic control circuit;

the second sample-and-hold module arranged to sample the second multiplexed voltage based on t_a, t_b, t_c, and t_d, and to provide a first lowest voltage; and

the third sample-and-hold module arranged to sample the first multiplexed voltage based on t_a, t_b, t_c, and t_d, and to provide a second lowest voltage, wherein a combination of the first lowest voltage and the second lowest voltage provides a lowest voltage V_valley of the hysteretic control circuit.

5. The circuit of claim 4, further comprising:

a differential amplifier that is arranged to receive V_lo and V_valley, and to provide a correction voltage V_COR in response to V_lo and V_valley.

6. The circuit of claim 5, wherein the differential amplifier is arranged to provide V_COR such that V_COR=(V_lo−

V_valley)/2.

7. The circuit of claim 4, wherein the first sample-and-hold module comprises:

one pair of sampling transistors that are activated based on phi_a and phi_b;

one pair of holding capacitors that are arranged to hold the sampled voltage; and

one pair of forwarding transistors that are arranged to provide the sampled voltage based on phi_b and phi_a.

8. The circuit of claim 4, wherein the second sample-and-hold module comprises:

one pair of sampling transistors that are activated based on t_a and t_b;

one pair of holding capacitors that are arranged to hold the sampled voltage; and

one pair of forwarding transistors that are arranged to provide the sampled voltage based on t_c and t_d.

9. The circuit of claim 4, wherein the third sample-and-hold module comprises:

one pair of sampling transistors that are activated based on t_b and t_c;

one pair of holding capacitors that are arranged to hold the sampled voltage; and

one pair of forwarding transistors that are arranged to provide the sampled voltage based on t_d and t_a.

10. The circuit of claim 2, wherein the hysteretic control circuit comprises:

a hysteretic feedback circuit that is arranged to provide a hysteretic feedback voltage in response to a reference voltage and the output voltage;

a comparator that is arranged to provide a corrected voltage in response to the correction voltage, the hysteretic feedback voltage, and at least one of the first multiplexed voltage and the second multiplexed voltage;

a frequency divider that is arranged to provide a first input voltage to a first dual phase driver and a second input voltage to a second dual phase driver in response to the corrected voltage;

the first dual phase driver that is arranged to provide the first multiplexed voltage in response to the first input voltage; and

the second dual phase driver that is arranged to provide the second multiplexed voltage in response to the second input voltage.

11. The circuit of claim 10, wherein the hysteretic control circuit further comprises:

an RC filter circuit that is arranged to receive the first multiplexed voltage and the second multiplexed voltage, and to provide the regulated output voltage.

12. The circuit of claim 10, wherein the first dual phase driver and the second dual phase driver each include a serially coupled inductor at their output stage.

13. The circuit of claim 10, wherein the comparator is arranged to add the correction voltage to the reference voltage from the hysteretic feedback circuit.

14. The circuit of claim 10, wherein the comparator is arranged to add the correction voltage to the output voltage from the hysteretic feedback circuit.

15. The circuit of claim 1, wherein transistors of the hysteretic voltage regulator, the timing logic circuit, and the sample and hold block include at least one of a PMOS FET and an NMOS FET.

16. A method for correcting an offset caused by multiplexing in a hysteretic regulation circuit, the method comprising:

sampling a first multiplexed voltage based on a first timing control voltage and a second timing control voltage;

sampling a second multiplexed voltage based on a first timing control voltage and a second timing control voltage in reverse order;

determining a low hysteretic limit voltage based on sampling the first multiplexed voltage and the second multiplexed voltage;

sampling the first multiplexed voltage based on a plurality of other timing control voltages;

sampling the second multiplexed voltage based on a plurality of the other timing control voltages;

determining a lowest voltage based on sampling the first multiplexed voltage and the second multiplexed voltage based on the other timing control voltages; and

determining a correction voltage based on the low hysteretic limit voltage and the lowest voltage.

17. The method of claim 16, further comprising combining the correction voltage with a reference voltage such that an offset component of an output voltage caused by multiplexing is substantially reduced.

18. The method of claim 16, further comprising combining the correction voltage with an output voltage such that an offset component of the output voltage caused by multiplexing is substantially reduced.

19. The method of claim 16, wherein determining the correction voltage comprises:

subtracting the lowest voltage from the low hysteretic limit voltage and dividing a resulting voltage by two.

20. A multiplexed hysteretic voltage regulation circuit, comprising:

a sample-and-hold circuit that is arranged to track a first phase and a second phase of a hysteretic voltage and to provide a correction voltage in response to a plurality of timing control voltages that are associated with the first phase and the second phase; and

a hysteretic control circuit that is arranged to provide a regulated output voltage based, in part, of the correction voltage, wherein the correction voltage is added to at least one of a reference voltage and the output voltage such that a DC offset of the output voltage that is caused by the multiplexing is corrected.