Fractional-N offset phase locked loop
First Claim
1. A phase locked loop system comprising:
- loop circuitry adapted to provide an output signal based on a divided reference signal;
combiner circuitry adapted to combine an initial fractional divide value and a modulation signal to provide a combined fractional divide value; and
a fractional-N divider adapted to fractionally divide a reference signal based on the combined fractional divide value to provide the divided reference signal such that the output signal is phase modulated.
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Accused Products
Abstract
A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.
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Citations
27 Claims
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1. A phase locked loop system comprising:
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loop circuitry adapted to provide an output signal based on a divided reference signal; combiner circuitry adapted to combine an initial fractional divide value and a modulation signal to provide a combined fractional divide value; and a fractional-N divider adapted to fractionally divide a reference signal based on the combined fractional divide value to provide the divided reference signal such that the output signal is phase modulated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of providing a modulated signal using a phase locked loop system comprising:
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providing an output signal based on a divided reference signal; combining an initial fractional divide value and a modulation signal to provide a combined fractional divide value; and fractionally dividing a reference signal based on the combined fractional divide value to provide the divided reference signal such that the output signal is phase modulated. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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Specification