High power, high linearity and low insertion loss single pole double throw transmitter/receiver switch

• US 7,098,755 B2
• Filed: 07/16/2003
• Issued: 08/29/2006
• Est. Priority Date: 07/16/2003
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Zhang, Shuyun, McMorrow, Robert J., Zhao, Yibing
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/620,395
• Publication Number:
  US 20050014473A1
• Time in Patent Office: 1,140 Days
• Field of Search: 333101-104, 333/262, 333/162, 327/408, 327/416, 327/427, 327/436
• US Class Current: 333/101
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A high performance single-pole-double-throw (SPDT) Transmitter/Receiver (T/R) FET switch utilizes a plurality of multi-gate FETs in series to realize low insertion loss, low harmonic distortion and high power handling capabilities. The SPDT switch consists of an antenna port, a transmitter branch coupled to a transmitter port through a plurality of multi-gate FETs in series and a receiver branch coupled to a receiver port through a plurality of multi-gate FETs in series. When a high power signal passes from the transmitter port to the antenna port through the transmitter branch, the receiver branch is required to be shut off electrically to prevent the high power signal from leaking to receiver port. This leakage can degrade the isolation of the switch and cause harmonic distortion. Furthermore, the transmitter branch is required to provide a resistance as small as possible to reduce the power loss when it passes through the transmitter branch to the antenna port. In the receiver branch, two of the gate metals in the multi-gate FETs are fabricated with gate sizes several times larger than the others. Furthermore, a heavily doped cap layer is utilized between the gate fingers in a multi-gate FET to reduce the channel resistance of FET, thereby lowering the insertion loss.

Claims

1. A switch comprising:

a plurality of dual-gate field effect transistors connected in series, each dual-gate field effect transistor including two gates, a source, and a drain;

one of said series connected dual-gate field effect transistors having a modified gate therein, said modified gate having a length that is of a different size from gate lengths of other series connected dual-gate field effect transistors.

2. The switch as claimed in claim 1, wherein said modified gate of said series connected dual-gate field effect transistor has a distance to its drain port that is less than a distance to its source port.

3. The switch as claimed in claim 1, wherein said modified gate of said series connected dual-gate field effect transistor has a distance to its source port that is less than a distance to its drain port.

4. The switch as claimed in claim 2, wherein gates of said other series connected dual-gate field effect transistors have a distance to its source port that is equal to a distance to its drain port.

5. The switch as claimed in claim 3, wherein gates of said other series connected dual-gate field effect transistors have a distance to its source port that is equal to a distance to its drain port.

6. The switch as claimed in claim 1, wherein a second series connected dual-gate field effect transistor has a modified gate therein that is of a different size from gates of other series connected dual-gate field effect transistors.

7. The switch as claimed in claim 1, wherein said dual-gate field effect transistors are high-electron-mobility-transistors.

8. The switch as claimed in claim 1, wherein the different gate sizes increase a parasitic capacitance within the switch.

9. A switch comprising:

a plurality of dual-gate field effect transistors connected in series, each dual-gate field effect transistor including two gates, a source, and a drain;

one of said series connected dual-gate field effect transistors having a modified gate therein that is of a different size from gates of other series connected dual-gate field effect transistors;

said dual-gate field effect transistors include a transistor connection segment between said gates and a heavily doped cap layer fabricated upon said transistor connection segment between said gates.

10. A high-electron-mobility-transistor, comprising:

two gate fingers;

a transistor connection segment between said gate fingers; and

a heavily doped cap layer fabricated upon said transistor connection segment between said gate fingers;

said gate fingers being of different sizes.

11. The high-electron-mobility-transistor as claimed in claim 10, wherein one of said gate fingers has a distance to its source port that is less than a distance to its drain port.

12. The high-electron-mobility-transistor as claimed in claim 10, wherein one of said gate fingers has a distance to its drain port that is less than a distance to its source port.

13. A radio frequency single pole double throw switch, comprising:

a receiver port;

a transmitter port;

an antenna port;

a receiver section connecting said receiver port to said antenna; and

a transmitter section connecting said transmitter port to said antenna;

said receiver section including a plurality of dual-gate field effect transistors connected in series, each dual-gate field effect transistor including two gates, a source, and a drain such that one of said series connected dual-gate field effect transistors has a modified gate therein, said modified gate having a length that is of a different size from gate lengths of other series connected dual-gate field effect transistors.

14. The radio frequency single pole double throw switch as claimed in claim 13, wherein a source of said modified gate transistor is connected to said receiver port.

15. The radio frequency single pole double throw switch as claimed in claim 13, wherein a drain of said modified gate transistor is connected to said antenna port.

16. The radio frequency single pole double throw switch as claimed in claim 13, wherein a second series connected dual-gate field effect transistor has a second modified gate therein that is of a different size from gates of other series connected dual-gate field effect transistors.

17. The radio frequency single pole double throw switch as claimed in claim 16, wherein a source of said modified gate transistor is connected to said receiver port and a drain of said second modified gate transistor is connected to said antenna port.

18. The radio frequency single pole double throw switch as claimed in claim 13, wherein said dual-gate field effect transistors are high-electron-mobility-transistors.

19. The radio frequency single pole double throw switch as claimed in claim 13, wherein said modified gate of said series connected dual-gate field effect transistor has a longer gate length and/or gate width than gates of said other series connected dual-gate field effect transistor.

20. The radio frequency single pole double throw switch as claimed in claim 13, wherein said modified gate of said series connected dual-gate field effect transistor has a distance to its drain port that is less than a distance to its source port.

21. The radio frequency single pole double throw switch as claimed in claim 13, wherein said modified gate of said series connected dual-gate field effect transistor has a distance to its source port that is less than a distance to its drain port.

22. The radio frequency single pole double throw switch as claimed in claim 20, wherein gates of said other series connected dual-gate field effect transistors have a distance to its source port that is equal to a distance to its drain port.

23. The radio frequency single pole double throw switch as claimed in claim 21, wherein gates of said other series connected dual-gate field effect transistors have a distance to its source port that is equal to a distance to its drain port.

24. The radio frequency single pole double throw switch as claimed in claim 13, wherein the different gate sizes increase a parasitic capacitance within the switch.

25. A radio frequency single pole double throw switch comprising:

a receiver port;

a transmitter port;

an antenna port;

a receiver section connecting said receiver port to said antenna; and

a transmitter section connecting said transmitter port to said antenna;

said receiver section including a plurality of dual-gate field effect transistors connected in series, each dual-gate field effect transistor including two gates, a source, and a drain such that one of said series connected dual-gate field effect transistors has a modified gate therein that is of a different size from gates of other series connected dual-gate field effect transistors;

said dual-gate field effect transistors include a transistor connection segment between said gates and a heavily doped cap layer fabricated upon said transistor connection segment between said gates.

26. A radio frequency single pole double throw switch comprising:

a receiver port;

a transmitter port;

an antenna port;

a receiver section connecting said receiver port to said antenna; and

a transmitter section connecting said transmitter port to said antenna;

said receiver section including,

a first receiver dual-gate high electron mobility transistor having gates of different lengths, and

a second receiver dual-gate high electron mobility transistor having gates of different lengths;

said transmitter section including a first transmitter dual-gate high electron mobility transistor having gates of different lengths and a second transmitter dual-gate high electron mobility transistor having gates of different lengths;

said first transmitter dual-gate high electron mobility transistor having a source, said source being connected to said receiver port and the drain of said second transmitter dual-gate high electron mobility transistor is connected to said antenna port.

27. The radio frequency single pole double throw switch as claimed in claim 26, wherein said transmitter section includes a first transmitter dual-gate high electron mobility transistor having gates of different lengths and a second transmitter dual-gate high electron mobility transistor having gates of different lengths.

28. The radio frequency single pole double throw switch as claimed in claim 26, wherein a first gate of said first receiver dual-gate high electron mobility transistor has a longer gate length and/or gate width than a second gate of said first receiver dual-gate high electron mobility transistor.

29. The radio frequency single pole double throw switch as claimed in claim 26, wherein a first gate of said first receiver dual-gate high electron mobility transistor has a distance to its drain port that is less than a distance to its source port.

30. The radio frequency single pole double throw switch as claimed in claim 26, wherein a first gate of said second receiver dual-gate high electron mobility transistor has a distance to its source port that is less than a distance to its drain port.

31. The radio frequency single pole double throw switch as claimed in claim 26, wherein the different gate lengths increase a parasitic capacitance within the switch.

32. The radio frequency single pole double throw switch claimed in claim 26, wherein the different gate lengths improve the linearity without impacting the ESD and EOS ruggedness.