Method, system and computer program product for efficiently utilizing limited resources in a graphics device

• US 7,098,921 B2
• Filed: 07/16/2001
• Issued: 08/29/2006
• Est. Priority Date: 02/09/2001
• Status: Expired due to Term

• Current Assignee: Activision Publishing Incorporated (Microsoft Corporation)
• Original Assignee: Activision Publishing Incorporated (Microsoft Corporation)
• Inventors: Nash, Reuel W, Young, Mark A, Labarre, Charles
• Primary Examiner(s): Tung, Kee M.
• Assistant Examiner(s): Singh, Dalip K.
• Application Number:
  US09/904,541
• Publication Number:
  US 20020109682A1
• Time in Patent Office: 1,870 Days
• Field of Search: 708/520, 345/522, 345/426, 345/1.1, 345/422, 345/505, 345/568, 345/558, 345/600, 345/685, 345/563, 345/419, 345/607, 712/239, 712/200, 712/248, 712/23, 712/215, 712/209, 712/216, 712/245, 711/141, 711/118, 714/35
• US Class Current: 345/506
• CPC Class Codes: G06F 9/223 Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A memory management system provides microcode instructions that are divided into multiple tuned phases and stored as separate modules inside a phase code depository. A microcode manager, containing a mode detector, sequence identifier, code loader, drawing data processor and phase executor, interacts with a microcode processor and the phase code depository. The mode detector evaluates a user request for a desired mode. In response to a command from the mode detector, the sequence identifier selects a correct phase sequence that is needed to implement the desired mode. The code loader transfers the phase sequence from the phase code depository to the microcode processor where it is stored in a microcode instruction memory. The memory address for each module within the phase sequence is written to a microcode data memory. The drawing data for the graphics mode is sent from the drawing data processor to the microcode processor, and the phase executor instructs the microcode processor to execute the phase sequence to render the desired mode by processing the drawing data. The resulting data is forwarded to another processor for additional microcode processing, vector processing, rasterization, or the like. The ability to select interchangeable phase modules to implement a desired mode reduces microcode memory requirements and allows easy integration and reuse of previously developed features among different games and other graphics software developers without having to rely on the type of platform.

Claims

1. A method for managing microcode, comprising the steps of:

evaluating a mode command to initiate or change a mode;

selecting a combination of functions and a sequence list forming a logical sequential concatenation of said functions, each function including microinstructions that, when executed, implement a phase or a sub-phase of said mode,

wherein said selecting said sequence list includes validating or optimizing said sequence list, wherein said validating or optimizing comprises searching for a faster version of a first partial sequence list selectable for said sequence list, wherein said faster version is a second partial sequence list; and

delivering said combination to a microcode processor according to said sequence list.

2. A method according to claim 1, wherein said selecting step further comprises the step of:

querying a storage medium to select said combination.

3. A method according to claim 1, further comprising the step of:

loading said combination into a microcode instruction memory.

4. A method according to claim 1, further comprising the step of:

loading said sequence list into a microcode data memory, wherein said sequence list includes a memory address to said combination.

5. A method according to claim 1, further comprising the step of:

executing said combination to implement said mode.

6. A method according to claim 5, further comprising the steps step of:

sending a result from said executing step to a processor for pixel processing or additional microcode processing.

7. A method according to claim 1, further comprising the step of:

sending drawing data to a microcode processor prior to said executing step.

8. A method according to claim 1, further comprising the step of:

sending drawing data to a microcode processor to render three dimensional graphics.

9. A method according to claim 1, further comprising the step of:

sending drawing data to a microcode processor to render an animation scene.

10. A method according to claim 1, further comprising the step of:

sending drawing data to a microcode processor to render a scene for a video game.

11. A system for managing microcode, comprising:

a mode detector for evaluating a mode command to initiate or change a mode; and

a sequence identifier for selecting a combination of functions and a sequence list forming a logical sequential concatenation of said functions, each function including microinstructions that, when executed, implement a phase or a sub-phase of said mode, wherein said sequence identifier is adapted to validate or optimize said sequence list by searching for a faster version of first partial sequence list selectable for said sequence list, wherein said faster version is a second partial sequence list.

12. A system of claim 11, further comprising:

a code loader for loading said combination into a microcode instruction memory.

13. A system of claim 11, further comprising:

a phase executor for commanding a microcode processor to execute said combination.

14. A system of claim 11, further comprising:

a drawing data processor for sending drawing data or input for drawing data to a microcode processor in response to said mode command.

15. A system of claim 11, further comprising:

a drawing data processor for sending drawing data or input for drawing data to a microcode processor to render a three dimensional model in response to said mode command.

16. A system of claim 11, further comprising:

a drawing data processor for sending drawing data or input for drawing data to a microcode processor to render an animation scene in response to said mode command.

17. A system of claim 11, further comprising:

a microcode data memory for storing said sequence list specifying a memory address to said combination.

18. A computer program product comprising a computer useable medium having computer readable program code means embedded in said medium for causing an application program to execute on a computer used to manage microcode, said computer readable program code means comprising:

first computer readable program code means for causing the computer to evaluate a mode command to initiate or change a mode;

second computer readable program code means for causing the computer to select a combination of functions and a sequence list forming a logical sequential concatenation of said functions, each function including microinstructions that, when executed, implement a phase or a sub-phase of said mode; and

third computer readable program code means for causing the computer to produce a validated or optimized said sequence list, wherein said third computer readable program code means includes computer readable program code means for causing the computer to search for a faster version of a first partial sequence list selectable for said sequence list, wherein said faster version is a second partial sequence list.

19. A computer program product according to claim 18, wherein said second computer readable program code means loads said combination into a microcode instruction memory.

20. A computer program product according to claim 18, further comprising:

fourth computer readable program code means for causing the computer to command a microcode processor to execute said combination.

21. A computer program product according to claim 18, further comprising:

fourth computer readable program code means for causing the computer to send drawing data or input for drawing data to a microcode processor in response to said mode command.

22. A computer program product according to claim 18, further comprising:

fourth computer readable program code means for causing the computer to send drawing data or input for drawing data to a microcode processor to render three-dimensional graphics in response to said mode command.

23. A computer program product according to claim 18, further comprising:

fourth computer readable program code means for causing the computer to store said sequence list specifying a memory address to said combination.

24. A method for managing microcode, comprising the steps of:

accessing a library of functions, each function including microinstructions that, when executed, implement a phase or a sub-phase of a graphics mode;

selecting a combination of functions from said library and a sequence list forming a logical sequential concatenation of said functions in response to a mode command to produce a desired mode mode;

wherein said selecting said sequence list includes validating or optimizing said sequence list, wherein said validating or optimizing comprises searching for a faster version of a first partial sequence list selectable for said sequence list, wherein said faster version is a second partial sequence list;

delivering said combination to a processor;

delivering drawing data to said processor; and

executing said combination to process said drawing data according to said sequence list and thereby render said desired mode.

25. A method according to claim 24, wherein said validating or optimizing step further comprises:

selecting a merger group from said library, wherein said merger group includes a combination of microinstructions that, when executed, implement a plurality of phases of a graphics mode.

26. A method according to claim 24, wherein said validating or optimizing step further comprises:

preprocessing data for said combination to calculate values used repetitively during said executing step.

27. A method according to claim 24, wherein said validating or optimizing step further comprises:

validating a loading state of a function selected for said combination.

28. A method according to claim 24, wherein said validating or optimizing step further comprises:

validating one or more of the functions to produce said combination.