Fault condition protection

• US 7,099,128 B2
• Filed: 11/07/2003
• Issued: 08/29/2006
• Est. Priority Date: 11/16/1998
• Status: Expired due to Term

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Lund, Leif, Balakrishnan, Balu, Djenguerian, Alex
• Primary Examiner(s): Williams, Hezron
• Assistant Examiner(s): Willoughby, Terrence
• Application Number:
  US10/703,702
• Publication Number:
  US 20040095694A1
• Time in Patent Office: 1,026 Days
• Field of Search: 361/18
• US Class Current: 361/18
• CPC Class Codes: B29C 2045/824 Accumulators
• CPC Class Codes: B29C 45/82 Hydraulic or pneumatic circuits
• CPC Class Codes: F16D 31/02 using pumps with pistons or plungers working in cylinders
• CPC Class Codes: H02H 7/1213 for DC-DC converters
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence

Abstract

A circuit protects a power conversion system with a feedback control loop from a fault condition. The circuit has an oscillator having an input for generating a signal with a frequency and a timer connected to the oscillator input and to the feedback control loop. The timer disables the oscillator after a period following the opening of the feedback control loop to protect the power conversion system.

Claims

1. A circuit, comprising:

switching means for controlling power delivered to an output of a power supply in response to a switching signal;

feedback input means for receiving a feedback signal representative of the output of the power supply, the feedback signal cycling periodically between a first state and a second state when the power supply operates normally and not cycling between the first and second states when the power supply is in a fault condition, the switching signal cycling separately from the cycling of the feedback signal; and

timing means coupled to the feedback input means to reduce power delivery to the output of the power supply after detection of the fault condition to protect the power supply from fault conditions.

2. The circuit of claim 1 wherein the timing means is operable to disable the switching means after a first period of existence of the fault condition and wherein the timing means is operable to enable the switching means after a second period.

3. The circuit of claim 2 wherein the switching means is alternately enabled for the first period and disabled for the second period when the fault condition exists.

4. The circuit of claim 3 wherein the switching means is enabled upon removal of the fault condition.

5. The circuit of claim 1 wherein the switching means comprises a power transistor.

6. The circuit of claim 1 wherein the timing means comprises a digital counter.

7. The circuit of claim 6 further comprising oscillating means coupled to the digital counter, the oscillating means to oscillate at a predetermined frequency.

8. The circuit of claim 7, wherein the oscillating means includes means for changing the predetermined frequency in response to a control input included in the oscillating means, the circuit further comprising a first current source coupled to the control input of the oscillating means to generate a first frequency.

9. The circuit of claim 8 further comprising a second current source coupled to the control input of the oscillating means to generate a second frequency.

10. The circuit of claim 9 wherein the digital counter includes an output coupled to the first and second current sources.

11. The circuit of claim 1 wherein the fault condition includes one or more of an output overload fault condition, an output short circuit fault condition and an open feedback control loop fault condition.

12. The circuit of claim 4 further comprising a capacitive means that is charged at a first rate from a first threshold to a second threshold to generate the first period, the capacitive means further being discharged from the second threshold to the first threshold at a second rate to generate the second period.

13. The circuit of claim 12 wherein the capacitive means is discharged to a voltage below the first threshold each time the feedback signal changes state.

14. The circuit of claim 12 wherein the capacitive means is discharged to a voltage below the first threshold each time the feedback signal enters the first state.