SRAM cell controlled by non-volatile memory cell
First Claim
1. A multi-purpose static random-access-memory cell controllable by a non-volatile memory cell comprising:
- a non-volatile memory cell having an output;
a static random-access-memory cell word line;
first and second complimentary static random-access-memory cell bit lines;
a first bit node;
a first access transistor coupled between the first bit node and the first complementary static random-access-memory cell bit line, the first access transistor having a gate coupled to the static random-access-memory cell word line;
a second bit node;
a second access transistor coupled between the second bit node and the second complementary static random-access-memory cell bit line, the second access transistor having a gate coupled to the static random-access-memory cell word line;
a first inverter having an input coupled to the first bit node and an output coupled to the second bit node;
a second inverter having an input coupled to the second bit node and an output coupled to the first bit node through a second transistor switch having a gate coupled to the control circuit;
a first transistor switch coupled between the output of the non-volatile memory cell and the first bit node;
a control circuit coupled to the gate of the first transistor switch.
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Accused Products
Abstract
First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.
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Citations
8 Claims
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1. A multi-purpose static random-access-memory cell controllable by a non-volatile memory cell comprising:
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a non-volatile memory cell having an output; a static random-access-memory cell word line; first and second complimentary static random-access-memory cell bit lines; a first bit node; a first access transistor coupled between the first bit node and the first complementary static random-access-memory cell bit line, the first access transistor having a gate coupled to the static random-access-memory cell word line; a second bit node; a second access transistor coupled between the second bit node and the second complementary static random-access-memory cell bit line, the second access transistor having a gate coupled to the static random-access-memory cell word line; a first inverter having an input coupled to the first bit node and an output coupled to the second bit node; a second inverter having an input coupled to the second bit node and an output coupled to the first bit node through a second transistor switch having a gate coupled to the control circuit; a first transistor switch coupled between the output of the non-volatile memory cell and the first bit node; a control circuit coupled to the gate of the first transistor switch. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A multi-purpose static random-access-memory cell controllable by a non-volatile memory cell comprising:
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a static random-access-memory cell coupled between first and second complimentary static random-access-memory cell bit nodes; a static random-access-memory cell word line; first and second complimentary static random-access-memory cell bit lines respectively coupled to the first and second complimentary static random-access-memory cell bit nodes through first and second access transistors, each of the first and second access transistors having a gate coupled to the static random-access-memory cell word line; a configuration word line; first and second complimentary configuration bit lines respectively coupled to the first and second complimentary static random-access-memory cell bit nodes through third and fourth access transistors, each of the third and fourth access transistors having a gate coupled to the configuration word line; a serial shift register stage having first and second complementary clock lines and coupled to the first and second complimentary static random-access-memory cell bit nodes; a non-volatile memory cell having an output; a complementing transistor coupled to the output of the non-volatile memory; a first transistor switch coupled between the output of the non-volatile memory cell and the first static random-access-memory cell bit node, the first transistor switch having a gate; a second transistor switch coupled between the output of the complementing transistor and the first static random-access-memory cell bit node, the second transistor switch having a gate; a control circuit coupled to the gates of the first and second transistor switches. - View Dependent Claims (8)
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Specification