Error recovery for nonvolatile memory

• US 7,099,194 B2
• Filed: 12/03/2004
• Issued: 08/29/2006
• Est. Priority Date: 12/12/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian, Tu, Loc
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Hien N
• Application Number:
  US11/003,545
• Publication Number:
  US 20050094440A1
• Time in Patent Office: 634 Days
• Field of Search: 365/185.18, 365/185.09, 365/185.24, 365/185.22, 365/185.29
• US Class Current: 365/185.18
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

An error recovery technique is used on marginal nonvolatile memory cells. A marginal memory cell is unreadable because it has a voltage threshold (VT) of less than zero volts. By biasing adjacent memory cells, this will shift the voltage threshold of the marginal memory cells, so that it is a positive value. Then the VT of the marginal memory cell can be determined. The technique is applicable to both binary and multistate memory cells.

Claims

1. A memory system, comprising:

an array of re-programmable non-volatile memory cell charge storage elements,

a plurality of control lines extending across the array, individual control lines being field coupled with both a plurality of charge storage elements thereunder and another plurality of charge storage elements under control lines adjacent thereto,

a reading circuit that reads the states of the charge storage elements under an addressed control line by applying a read voltage to the addressed control line and either a second or third voltage to the control lines adjacent thereto, the second and third voltages being different from each other, and

a controller operably connected with the control lines and the reading circuit to cause data to be read from the charge storage elements under the addressed control line while the second voltage is applied to the adjacent control lines and to check the read data for error, and, as a response to discovery of an error in the read data, to cause the data to then be re-read from the charge storage elements under the addressed control line with the third voltage applied to the adjacent control lines.

2. The memory system of claim 1, wherein the reading circuit reads one of more than two states of the charge storage elements, thereby reading more than one bit of data in the individual charge storage elements.

3. The memory system of claim 1, wherein the memory cell array includes a plurality of strings of series connected memory cells and the control lines individually extend across one storage element of each of a plurality of strings.

4. The memory system of claim 3, wherein the controller operates to apply the second or third voltage to the control lines closest to the addressed control line and on opposite sides thereof.

5. The memory system of claim 1, wherein the third voltage is greater than the second voltage by at least 0.25 volt.

6. The memory system of claim 1, wherein the controller operates to check the read data for error by use of an error correction code.

7. The memory system of claim 6, wherein the controller, if the check discovers an error in the read data, utilizes the error correction code to correct the read data if the error correction code is able to do so but if the error correction code is unable to correct the errors then causes the data to be re-read from the charge storage elements under the addressed control line with the third voltage applied to the adjacent control lines.

8. The memory system of claim 1, wherein the charge storage elements are conductive floating gates.

9. A method of reading data stored as levels of charge in a plurality of re-programmable non-volatile memory cells, comprising:

initially reading the data stored in a first group of a plurality of memory cells by applying a read voltage to gates of the memory cells of the first group, and applying a second voltage to gates of the memory cells of a second group located adjacent the first group in order not to read the data stored in the memory cells of the second group,

checking the data read from the first group of memory cells for any data errors by use of an error correction code, and

in response to any data error,

(a) if the error correction code is able to recover the correct data, utilizing the error correction code to correct the data error, or

(b) if the error correction code is unable to recover the correct data, re-reading the data stored in the memory cells of the first group of memory cells by applying a third voltage to gates of the memory cells of the second group that is different from the second voltage in order to alter threshold voltages of the memory cells of the first group on account of field coupling between memory cells of the first and second groups.