Multi-level pulse amplitude modulation receiver
First Claim
1. Apparatus for processing an M-level signal, M>
- 2, comprising;
(a) a plurality of data slicers, each adapted to data sample the M-level signal relative to a threshold level between a different adjacent pair of symbol levels;
(b) two or more edge slicers, each adapted to edge sample the M-level signal relative to a threshold level between a different adjacent pair of symbol levels;
(c) a clock generator adapted to generate at least one clock signal based on outputs from the two or more edge slicers, wherein the at least one clock signal determines the timing of the data sampling of the M-level signal by at least one of the plurality of data slicers.
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Abstract
Multiple-level phase amplitude (M-PAM) clock and data recovery circuitry uses information from multiple phase detectors to generate one or more data sampling clocks that are optimized for each of the data slicers. One possible 4-PAM implementation includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The phase detector outputs are combined (e.g., via weighted voting, weighted average, minimum error, and/or minimum variance) to determine an optimized phase estimate for the clock used to sample the data at all three data slicers. Another 4-PAM implementation similarly includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The mid-amplitude edge slicer and phase detector are used in combination with the VCO to generate a central phase while a multiple-tap delay line provides N phase variants before and after the central phase. Information from the non-mid-amplitude edge slicers and phase detectors is used to choose a phase from among the phase variants that best suits the other data slicers. In yet another implementation, a single edge slicer, single phase detector, and single VCO is used to generate a key clock which is used by the edge slicer to track the symbol timing. A clock generator provides a single optimized clock (that is offset from the key clock) that is used by the data slicers. Bit error rates from the data slicers are used to adjust the offset until the data slicer clock is optimized with respect to all the slicers. Alternatively, multiple clocks are generated via offsets from the key clock, each being optimized to the data slicer group that it drives.
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Citations
18 Claims
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1. Apparatus for processing an M-level signal, M>
- 2, comprising;
(a) a plurality of data slicers, each adapted to data sample the M-level signal relative to a threshold level between a different adjacent pair of symbol levels; (b) two or more edge slicers, each adapted to edge sample the M-level signal relative to a threshold level between a different adjacent pair of symbol levels; (c) a clock generator adapted to generate at least one clock signal based on outputs from the two or more edge slicers, wherein the at least one clock signal determines the timing of the data sampling of the M-level signal by at least one of the plurality of data slicers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- 2, comprising;
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10. A method for processing an M-level signal, M>
- 2, comprising;
(a) data sampling the M-level signal relative to each of a plurality of threshold levels, each threshold level between a different adjacent pair of symbol levels in the M-level signal; (b) edge sampling the M-level signal relative to each of two or more threshold levels using two or more edge slicers, each threshold level between a different adjacent pair of symbol levels; and (c) generating at least one clock signal based on outputs from the two or more edge slicers, wherein the at least one clock signal determines the timing of the data sampling of at least one of the M-level signals. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
- 2, comprising;
Specification