Interprocess communication protocol system

• US 7,099,949 B1
• Filed: 10/25/2000
• Issued: 08/29/2006
• Est. Priority Date: 10/23/1995
• Status: Expired due to Fees

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Vanhoof, Jan, Rompaey, Karl Van, Vernalde, Serge, Wouters, Maryse
• Primary Examiner(s): Wiley, David
• Assistant Examiner(s): DENNISON, JERRY B
• Application Number:
  US09/696,836
• Time in Patent Office: 2,134 Days
• Field of Search: 709230-237
• US Class Current: 709/230
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04L 69/03 Protocol definition or specification protocol conformance testing H04L1/244
• CPC Class Codes: H04W 80/00 Wireless network protocols or protocol adaptations to wireless operation
• CPC Class Codes: H04W 92/00 Interfaces specially adapted for wireless communication networks

Abstract

The interprocess communication protocol system provides a generic communication system for communication between specified processes in a complex digital system. In accordance with the interprocess communication protocol, a group of pre-defined communication signals are defined, to which all communications between the processes conform. Interface hardware is disclosed to provide communication between processes. In addition, the communication protocol can be designed into the process as and integral portion of the processes.

Claims

1. A method for defining a system specification for a digital system, said method comprising the steps of:

partitioning said system into a plurality of processes, each of the processes having a defined behavior and each of the processes having at least one control thread;

defining separately from said processes a single data independent communication protocol for communication within said digital system and between said processes;

configuring data communication interfaces in the form of communication input ports and communication output ports for each of the processes, the communication ports forming memory free communication channels, said step of configuring data communication interfaces involving defining communication interfaces with input ports of a first process and output ports to provide unidirectional, point-to-point connections between input ports of a first process and output ports of a second process, said input ports and said output ports being part of the associated processes, said processes implemented in C, Silage or VHDL language; and

combining the results of the steps of partitioning, defining and configuring to define specifications for said plurality of processes to form said system specification.

2. A method of implementing a digital system comprising the steps of:

partitioning said system into a plurality of processes, each process having a defined behavior and with at least one control thread;

defining separately from said processes, a single data independent communication protocol for communication within said digital system and between said processes;

organizing said data communication protocol with input and output ports for said processes, said ports using memory free communication channels; and

designing a plurality of processors to implement said process, said step of designing processors comprising the step of specifying a processor having specification which conforms to the processes implemented, said processor comprising a programmable digital signal processor, wherein said plurality of specifications are selected from a group consisting of Silage descriptions, C descriptions, VHDL process descriptions.

3. A method of implementing a digital system comprising the steps of:

partitioning said system into a plurality of processes, each process having a defined behavior and with at least one control thread;

defining separately from said processes, a single data independent communication protocol for communication within said digital system and between said processes;

organizing said data communication protocol with input and output ports for said processes, said ports using memory free communication channels implemented as interrupt driven I/O; and

designing a plurality of processors to implement said process, said step of designing processors comprising the step of specifying a processor having specification which conforms to the processes implemented.

4. A method of implementing a digital system comprising the steps of:

partitioning said system into a plurality of processes, each process having a defined behavior and with at least one control thread;

defining separately from said processes, a single data independent communication protocol for communication within said digital system and between said processes;

organizing said data communication protocol with input and output ports for said processes, said ports using memory free communication channels, said communication channels implemented in integrated circuit form for communications between a first processor and a second processor across said channel, said first and second processors selected from one or more of a plurality of processor types, wherein said plurality of processor types consists of Cathedral-III processors, ARM processors and VHDL generated processors; and

designing a plurality of processors to implement said process, said step of designing processors comprising the step of specifying a processor having specification which conforms to the processes implemented, said processor comprising a programmable, general purpose processor.

5. A method of implementing a digital system comprising the steps of:

partitioning said system into a plurality of processes, each process having a defined behavior and with at least one control thread, said step of partitioning involving defining a library of auxiliary processes to simulate the digital system, the library of processes selected from a plurality of processes consisting of one or more of an interactive I/O process, a file I/O process, a graphical output process, a channel duplicator process, a channel merging process, a FF process, a slider process, a button process, a first-in, first-out buffer process, an ARM processor, a digital to analog conversion process and an analog to digital conversion process;

defining separately from said processes, a single data independent communication protocol for communication within said digital system and between said processes;

organizing said data communication protocol with input and output ports for said processes, said ports using memory free communication channels; and

designing a plurality of processors to implement said process, said step of designing processors comprising the step of specifying a processor having specification which conforms to the processes implemented, wherein said processor comprises a programmable digital signal processor.