Multi-core communications module, data communications system incorporating a multi-core communications module, and data communications process

• US 7,099,983 B2
• Filed: 11/25/2002
• Issued: 08/29/2006
• Est. Priority Date: 11/25/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Emerson, Steven M., Hammitt, Gregory F., Kopacek, Steven G.
• Primary Examiner(s): Atrve, Glenn A.
• Assistant Examiner(s): King, Justin
• Application Number:
  US10/303,589
• Publication Number:
  US 20040103230A1
• Time in Patent Office: 1,373 Days
• Field of Search: 710/315, 710/317, 710/307, 710/56, 710/306, 370/402
• US Class Current: 710/306
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/4009 with data restructuring
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A communications module for a data communications system having a plurality of data processors comprises a plurality of ports, each coupled to a respective one of the data processors. An address table associates addresses of a memory space to addresses of the data processors. The memory space may include addressable FIFOs, SRAM memory and/or flag registers. In the case of FIFOs, a counter coupled to the FIFO supplies a flag or ready signal indicating the not-full or not-empty status of the respective FIFO, which is supplied to a master device that is writing data to the FIFO or that is reading data from the FIFO so that the writing master device will write only when the FIFO is not full and the reading master device will read only when the FIFO is not empty.

Claims

1. A data communications system comprising:

a first data communications bus, a plurality of first slave devices coupled to the first data communications bus and a plurality of first master devices coupled to the first data communications bus to initiate data communications in a first format between each respective first master device and a selected first slave device, each first master device having a respective first master device address in the first format;

a second data communications bus, a plurality of second slave devices coupled to the second data communications bus and a plurality of second master devices coupled to the second data communications bus to initiate data communications in a second format between each respective second master device and a selected second slave device, each second master device having a respective second master device address in the second format, the first and second formats being incompatible; and

a communications module coupled as a slave device to each of the first and second data communications buses, the communications module comprising;

a memory device having a plurality of individually addressable locations for storing data from a transmitting first or second master device at an addressable location identified by a second address,

an address table associated with each of the addressable locations for associating addresses of the respective addressable location to addresses of respective first and second master devices, the address table being responsive to a first address to associate the second address and a third address to the first address, the first address being the address of a receiving first or second master or slave device in the format of the transmitting first or second master device, the third address being the address of the receiving first or second master or slave device in the format of the receiving first or second master or slave device, and

a multiplexer responsive to the third address from a receiving first or second master or slave device for transmitting data between the location in the memory device identified by the second address and the respective first or second data communications bus.

2. The data communications system of claim 1, wherein the memory device comprises a random access memory.

3. The data communications system of claim 1, wherein the memory device comprises:

a plurality of addressable first-in, first-out (FIFO) memories.

4. The data communications system of claim 3, further comprising:

a first counter coupled to each FIFO, the first counter being responsive to the respective FIFO not being full to provide a not-full status flag, and

the communications module being responsive to the not-full status flag to enable at least one of the first and second master and slave devices to transmit data on a respective data communications bus to the communications module for storage in the respective FIFO.

5. The data communications system of claim 4, further comprising:

a second counter coupled to each FIFO, the second counter being responsive to the respective FIFO not being empty to provide a not-empty status flag, and

the communications module being responsive to the not-empty status flag to enable at least one of the first and second master and slave devices that to receive data on a respective data communications bus from the respective FIFO.

6. The data communications system of claim 3, further comprising:

a second counter coupled to each FIFO, the second counter being responsive to the respective FIFO not being empty to provide a not-empty status flag, and

the communications module being responsive to the not-empty status flag to enable at least one of the first and second master and slave devices to receive data on a respective data communications bus from the respective FIFO.

7. The data communications system of claim 1, further comprising:

an arbiter coupled to the multiplexer for arbitrating access to the memory device by the first and second data communications buses.

8. The data communications system of claim 1, wherein at least the first data communications bus operates in a format different from an operating data format of the communications module, the communications module further includes a first port coupled to the first data communications bus and a second port coupled to the second data communications bus, the first port being operable to transform data between the format of the first data communications bus and the format of the communications module.

9. A communications module for a data communications system having a plurality of data processors capable of communicating data, the communications module comprising:

A plurality of ports, each port arranged to be coupled to at least a respective one of the data processors, at least a first of the plurality of ports being coupled to at least a first data processor that operates in a first format and at least a second of the plurality of ports being coupled to at least a second data processor that operates in a second format that is incompatible with the first format, the second data processor having an address in the second format;

A memory device having a plurality of individually addressable locations for storing data from a transmitting data processor at an addressable location identified by a second address, each of the addressable locations being addressable by at least two of the data processors, at least one of the addressable locations being addressable by the first and second data processors,

An address table associated with each of the addressable locations for associating addresses of the respective addressable location to addresses of respective data processors, the address table being responsive to a first address to associate the second address and a third address to the first address, the first address being the address of a receiving first or second data processor in the format of the transmitting first or second data processor, the third address being the address of the receiving first or second data processor in the format of the receiving first or second data processor, and

A multiplexer responsive to the third address from a receiving first or second data processor for transmitting data between the location in the memory device identified by the second address and the respective receiving data processor.

10. The communications module of claim 9, wherein the memory device comprises:

a plurality of addressable first-in, first-out (FIFO) memories.

11. The communications module of claim 10, wherein the first data processor is operable to communicate data to the module for storage in a respective FIFO, the module further comprising:

a first counter coupled to each FIFO, the first counter being responsive to the respective FIFO not being full to provide a not-full status flag, and

the first port being responsive to the not-full status flag to enable the first data processor to transmit data for storage in the respective FIFO.

12. The communications module of claim 11, wherein the second data processor is operable to receive data stored in the respective FIFO, the module further comprising:

a second counter coupled to each FIFO, the second counter being responsive to the respective FIFO not being empty to provide a not-empty status flag, and

the second port being responsive to the not-empty status flag to enable the second data processor to receive data from the respective FIFO.

13. The communications module of claim 10, wherein the second data processor is operable to receive data stored in the respective FIFO, the module further comprising:

a second counter coupled to each FIFO, the second counter being responsive to the respective FIFO not being empty to provide a not-empty status flag, and

the second port being responsive to the not-empty status flag to enable the second data processor to receive data from the respective FIFO.

14. The communications module of claim 10, wherein the memory device includes a random access memory and a flag register.

15. The communications module of claim 9, further comprising:

an arbiter coupled to the multiplexer for arbitrating access to the memory device by the data processors.

16. The communications module of claim 13, wherein at least the first data processor operates in a format different from an operating data format of the module, each port coupled to a data processor that operates in a format different from the module being operable to transform data between the format of the respective data processor and the format of the module.

17. A process of communicating data between a first data communications device coupled to a first data bus operable to communicate in a first format and a second data communications device coupled to a second data bus operable to communicate in a second format, the second data communications device having an address in the second format, the first and second formats being incompatible, the process comprising steps of:

a) operating the first data communications device to transmit a first address to a communications module coupled as a slave device to each of the first and second data buses, the first address being an address of the second data communications device in the first format, the communications module having a plurality of individually addressable locations,

b) operating the first data communications device to transmit data to the communications module,

c) associating the first address to a second address that identifies an addressable location in the communications module,

d) storing the data at the addressable location in the communication module identified by the second address,

e) associating a third address to the first address, the third address being in the second format,

f) operating the second data communications device to transmit a request, using the third address, to the communications module to transmit data stored in the communication module at the addressable location identified by the second address, and

g) operating the communications module in response to receipt of the request to transmit data from the addressable location in the communication module to the second data communications device.

18. The process of claim 17, further including a step of:

h) arbitrating use of the communications module by the first and second data communications devices.

19. The process of claim 18, wherein the first and second data communication devices each includes a bus having a plurality of master devices and a plurality of slave devices connected thereto.

20. The process of claim 17, wherein each of the first and second data buses comprises a plurality of master devices, at least one slave device and a bus arbiter arbitrating use of the respective data bus, wherein the communication module is operated as a slave device to both the first and second data buses.