RAID memory system
First Claim
1. A memory system comprising:
- a host integrated circuit;
a first memory controller having at least one associated memory defining a first address space;
a second memory controller having at least one associated memory defining a second address space;
a parity memory for storing parity information associated with data stored in the memories associated with the first and second memory controllers; and
a controller for the storing data in the parity memory, the controller configured to store parity data associated with data stored in the memory associated with the first memory controller in an interleaved fashion with data stored in the memory associated with the second memory controller.
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Accused Products
Abstract
Embodiments of the present invention are broadly directed to a memory system. In one embodiment, a first data memory is coupled to a first memory controller and a second data memory is coupled to a second memory controller. A parity memory is coupled to a parity controller, the parity controller being directly coupled to both the first memory controller and the second memory controller. Parity data control logic is configured to store and retrieve parity information associated with data stored in both the first data memory and the second data memory, the parity data control logic configured to interleave within the parity memory parity data associated with data stored in the first data memory with parity data associated with data stored in the second data memory.
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Citations
17 Claims
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1. A memory system comprising:
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a host integrated circuit; a first memory controller having at least one associated memory defining a first address space; a second memory controller having at least one associated memory defining a second address space; a parity memory for storing parity information associated with data stored in the memories associated with the first and second memory controllers; and a controller for the storing data in the parity memory, the controller configured to store parity data associated with data stored in the memory associated with the first memory controller in an interleaved fashion with data stored in the memory associated with the second memory controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory system comprising:
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first data memory coupled to a first memory controller; second data memory coupled to a second memory controller; a parity memory coupled to a parity controller, the parity controller being directly coupled to both the first memory controller and the second memory controller; parity data control logic configured to store and retrieve parity information associated with data stored in both the first data memory and the second data memory, the parity data control logic configured to interleave within the parity memory parity data associated with data stored in the first data memory with parity data associated with data stored in the second data memory. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method for managing parity information associated with a plurality of memory controllers comprising:
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generating first parity information associated with data to be stored in a first data memory coupled to a first memory controller; generating second parity information associated with data to be stored in a second data memory coupled to a second memory controller; storing the first and second parity information in a parity memory coupled to a parity controller, the first and second parity information being stored in an interleaved fashion within the parity memory. - View Dependent Claims (17)
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Specification