Port independent data transaction interface for multi-port devices

• US 7,100,002 B2
• Filed: 09/16/2003
• Issued: 08/29/2006
• Est. Priority Date: 09/16/2003
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Denali Software Incorporated (Cadence Group)
• Inventors: Pal, Samitinjoy, Espinoza, Anne, Shrader, Steven, McKeon, Michael
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): PATEL, KAUSHIKKUMAR M
• Application Number:
  US10/663,327
• Publication Number:
  US 20050060501A1
• Time in Patent Office: 1,078 Days
• Field of Search: None
• US Class Current: 711/149
• CPC Class Codes: G06F 13/1673 using buffers

Abstract

A port independent data transaction interface for multi-port devices is provided. The port independent data transaction interface includes a command channel that receives command data and a source id. The source id indicates a source device that transmitted the command data. In addition, a data-in channel is included that receives write data and a write source id. Similar to the source id, the write source id indicates a source device that transmitted the write data. The port independent data transaction interface further includes a data-out channel that provides read data and a read id. The read id indicates a source device that transmitted a read command corresponding to the read data. The port independent data transaction interface utilizes the source id to associate command data with corresponding write data and read data.

Claims

1. A port independent data transaction interface for multi-port devices, comprising:

a command channel that receives command data and a source id, the source id indicating a source device that transmitted the command data;

a data-in channel having a data-in transfer storage that receives write data and a write source id, the write source id indicating a source device that transmitted the write data, the data-in channel having a data path that circumvents the data-in transfer storage; and

a data-out channel that provides read data and a read id, the read id indicating a source device that transmitted a read command corresponding to the read data.

2. A port independent data transaction interface as recited in claim 1, wherein the source id is utilized to associate command data with corresponding write data.

3. A port independent data transaction interface as recited in claim 2, wherein the write data transmitted to the data-in channel and corresponding command data transmitted to the command channel are processed when transmitted during different clock signals.

4. A port independent data transaction interface as recited in claim 1, wherein the command channel further receives length data indicating a size of data corresponding to the command data, wherein the length data can indicate an arbitrary data size.

5. A port independent data transaction interface as recited in claim 4, wherein the command channel further receives address data indicating an address associated with data corresponding to the command data, wherein the address data can indicate an arbitrary starting location.

6. A port independent data transaction interface as recited in claim 1, wherein the command channel further receives a priority value indicating a priority level of the command data.

7. A port independent data transaction interface as recited in claim 6, wherein command data is processed based on an associated priority value.

8. A multi-port memory controller having port independent data transaction interface, comprising:

a command transfer storage that receives command data and a source id, the source id indicating a source device that transmitted the command data;

a data-in transfer storage that receives write data and a write source id, the write source id indicating a source device that transmitted the write data, the data-in transfer storage being in communication with a separate data-in signal for each source device coupled to the multi-port memory controller, each data-in signal being further coupled to a data path that circumvents the data-in transfer storage; and

a data-out transfer storage that provides read data and a read id, the read id indicating a source device that transmitted a read command corresponding to the read data.

9. A multi-port memory controller as recited in claim 8, wherein the source id is utilized to associate command data with corresponding write data.

10. A multi-port memory controller as recited in claim 9, wherein the write data transmitted to the data-in transfer storage and corresponding command data transmitted to the command transfer storage are processed when transmitted during different clock signals.

11. A multi-port memory controller as recited in claim 8, wherein the command transfer storage further receives a priority value indicating a priority level of the command data.

12. A multi-port memory controller as recited in claim 11, wherein command data is processed based on an associated priority value.

13. A method for performing data transactions in a multi-port system, comprising the operations of:

receiving command data and a source id on a command channel during a first clock cycle, the source id indicating a source device that transmitted the command data;

receiving write data and a write source id at a data-in transfer storage via a data-in channel during a second clock cycle, the write source id indicating a source device that transmitted the write data;

associating the command data with the write data based on the source id and the write source id;

transmitting both the command data and write data from the data-in transfer storage to a processing circuit for further processing during a third clock cycle when the data-in transfer storage has unused storage capacity; and

transmitting both the command data and write data via a data path that circumvents the data-in transfer storage when the data-in storage is full.

14. A method as recited in claim 13, wherein the first clock cycle, second clock cycle, and third clock cycle are each separated by a plurality of clock cycles.

15. A method as recited in claim 13, further comprising the operation of providing read data and a read id on a data-out channel during a fourth clock cycle, the read id indicating a source device that transmitted a read command corresponding to the read data.

16. A method as recited in claim 15, further comprising the operation of associating command data with the read data based on a source id and the read id.

17. A method as recited in claim 13, further comprising the operation of receiving a priority value on the command channel during the first clock cycle, wherein command data is processed based on an associated priority value.