Adaptive power control

• US 7,100,061 B2
• Filed: 01/18/2000
• Issued: 08/29/2006
• Est. Priority Date: 01/18/2000
• Status: Expired due to Term

• Current Assignee: Semcon IP Inc. (Quest Patent Research Corporation)
• Original Assignee: Transmeta Corporation (Novafora, Inc.)
• Inventors: Klayman, Keith, Lawrence, Thomas, Read, Andrew, Halepete, Sameer, Anvin, H. Peter, Chen, Zongjian, D'Souza, Godfrey P., Fleischmann, Marc
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US09/484,516
• Publication Number:
  US 20020116650A1
• Time in Patent Office: 2,415 Days
• Field of Search: 713300-340
• US Class Current: 713/322
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.

Claims

1. A method for controlling power consumption of a computer processor on a chip comprising the steps of:

determining a maximum allowable power consumption level from an operating condition of the processor,

said computer processor determining a maximum frequency which provides power not greater than the allowable power consumption level,

said computer processor determining a minimum voltage which allows operation at the maximum frequency determined, and

dynamically changing the power consumption of the processor by changing frequency and voltage, respectively, to the maximum frequency and the minimum voltage determined, wherein said dynamically changing the power consumption comprises executing instructions in said computer processor while changing voltage at which said computer processor is operated.

2. The method of claim 1, wherein said dynamically changing the power consumption comprises increasing voltage prior to increasing frequency.

3. The method of claim 1, wherein said dynamically changing the power consumption comprises lowering frequency prior to lowering voltage.

4. The method of claim 3, wherein dynamically changing the power consumption further comprises:

executing instructions in said computer processor while lowering voltage at which said computer processor is operated.

5. The method of claim 1, wherein said dynamically changing the power consumption comprises:

executing said instructions in said computer processor while lowering voltage at which said computer processor is operated.

6. The method of claim 1, wherein said dynamically changing the power consumption comprises concurrently generating a plurality of frequencies.

7. The method of claim 1, wherein said operating condition of the processor is internal to the processor.

8. A computing device comprising:

a power supply furnishing selectable output voltages,

a clock frequency source,

a central processor including;

a processing unit for providing values indicative of operating conditions of the central processor, and

a clock frequency generator receiving a clock frequency from the clock frequency source and providing one of a plurality of selectable output clock frequencies to the processing unit;

means for detecting the values indicative of operating conditions of the central processor and causing the power supply and clock frequency generator to furnish an output clock frequency and voltage level for the central processor and to generate concurrently frequencies which are selected for optimum operation of a plurality of functional units of the computing device; and

means for executing instructions in said central processor while changing voltage at which said central processor is operated.

9. A computing device as claimed in claim 8 in which the means for detecting the values indicative of operating conditions of the central processor comprises control software for determining an output clock frequency and voltage level for the central processor adapted to conserve power while maintaining an effective execution rate.

10. A method for controlling the power used by a computer comprising the steps of:

utilizing control software dedicated to a central processor to measure the operating characteristics of the central processor of the computer,

determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and

changing the operating characteristics of the central processor to a level commensurate with the operations being conducted in which;

the step of determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted comprising utilizing the control software to determine desirable voltages and frequencies for the operation of the central processor based on the measured operating characteristics, and

the step of changing the operating characteristics of the central processor to a level commensurate with the operations being conducted comprises;

providing signals;

for controlling voltages furnished by a programmable power supply to the central processor,

for controlling frequencies furnished by the central processor to the central processor, and

providing signals for controlling frequencies furnished by the central processor to other functional units of the computer; and

executing instructions in said central processor while changing voltage at which said central processor is operated.

11. A computer comprising:

a power supply furnishing selectable output voltages,

a clock frequency source,

a bus,

system memory,

a central processor including;

a processing unit for providing values indicative of operating conditions of the central processor, and

a clock frequency generator receiving a clock frequency from the clock frequency source and providing a plurality of selectable output clock frequencies to the processing unit; and

means for detecting the values indicative of operating conditions of the central processor and causing the power supply and clock frequency generator to furnish an output clock frequency and voltage level for the central processor and to generate concurrently frequencies which are selected for optimum operation of a plurality of functional units of the computing device including system memory, wherein the means for detecting the values indicative of operating conditions of the central processor is further for causing execution of instructions in said central processor while changing voltage at which said central processor is operated.

12. A computer as claimed in claim 11 in which the means for detecting the values indicative of operating conditions of the central processor comprises control software for determining an output clock frequency and voltage level for the central processor adapted to conserve power while maintaining an effective execution rate.

13. A computing device as claimed in claim 11 in which the means for detecting the values indicative of operating conditions of the central processor causes the clock frequency generator to generate frequencies with are selected for optimum operation of system memory.

14. A computing device as claimed in claim 11 in which the means for detecting the values indicative of operating conditions of the central processor causes the clock frequency generator to generate frequencies which are selected for optimum operation of the bus.

15. A method of controlling a computer processor, comprising:

monitoring operating conditions internal to said computer processor;

determining a frequency and a voltage at which to operate said computer processor, based on said internal operating conditions; and

implementing the determined frequency and voltage, wherein said implementing comprises;

executing instructions in said computer processor while changing voltage at which said computer processor is operated.

16. The method of claim 15 wherein said monitoring comprises said computer processor monitoring operating conditions internal to said computer processor.

17. The method of claim 15, wherein said implementing comprises lowering frequency at which said computer processor is operated.

18. The method of claim 17, wherein said changing voltage comprises lowering voltage at which said computer processor is operated.

19. The method of claim 18, wherein said lowering voltage occurs after said lowering frequency.

20. The method of claim 15, wherein said implementing comprises:

increasing frequency at which said computer processor is operated.

21. The method of claim 20, wherein said changing voltage comprises increasing voltage at which said computer processor is operated.

22. The method of claim 21, wherein said increasing voltage occurs prior to said increasing frequency.

23. A method of controlling a computer processor, comprising:

monitoring idle time of said computer processor;

said computer processor determining a frequency and a voltage at which to operate said computer processor, based on said idle time; and

implementing the determined frequency and voltage, wherein said implementing comprises executing instructions in said computer processor while changing voltage at which said computer processor is operated.

24. The method of claim 23, wherein said implementing comprises:

lowering frequency at which said computer processor is operated prior to lowering voltage at which said computer processor is operated.

25. The method of claim 24, wherein said implementing further comprises:

increasing voltage at which said computer processor is operated prior to increasing frequency at which said computer processor is operated.

26. The method of claim 24, wherein said implementing further comprises:

executing instructions in said computer processor while lowering voltage at which said computer processor is operated.

27. The method of claim 23, wherein said implementing comprises:

increasing voltage at which said computer processor is operated prior to increasing frequency at which said computer processor is operated.

28. The method of claim 23, wherein said monitoring idle time comprises monitoring internal data of said computer processor.

29. The method of claim 23, wherein said implementing comprises:

executing instructions in said computer processor while lowering voltage at which said computer processor is operated.

30. A method of controlling a computer processor, comprising:

monitoring a state of said computer processor;

said computer processor determining a frequency and a voltage at which to operate said computer processor, based on said state; and

implementing the determined frequency and voltage, wherein said implementing comprises executing instructions in said computer processor while changing voltage at which said computer processor is operated.

31. The method of claim 30, wherein said state comprises a sleep state.

32. The method of claim 31, wherein said monitoring further comprises monitoring a halt state of said computer processor.

33. The method of claim 30, wherein said state comprises a halt state.

34. The method of claim 30, wherein said implementing comprises:

lowering frequency at which said computer processor is operated prior to lowering voltage at which said computer processor is operated.

35. The method of claim 34, wherein said implementing further comprises:

increasing voltage at which said computer processor is operated prior to increasing frequency at which said computer processor is operated.

36. The method of claim 34, wherein said implementing further comprises:

executing instructions in said computer processor while lowering voltage at which said computer processor is operated.

37. The method of claim 30, wherein said implementing comprises:

increasing voltage at which said computer processor is operated prior to increasing frequency at which said computer processor is operated.

38. The method of claim 30, wherein said implementing comprises:

executing instructions in said computer processor while lowering voltage at which said computer processor is operated.

39. A method of managing power consumption comprising:

monitoring internal conditions of a computer processor;

based on said internal conditions, determining an allowable power consumption level;

a computer processor determining a voltage-frequency pair for said allowable power consumption level; and

dynamically changing power consumption of the computer processor by implementing said voltage-frequency pair, wherein said dynamically changing power consumption comprises changing voltage at which said computer processor is operated while executing instructions in said computer processor.

40. The method of claim 39, wherein said dynamically changing power consumption comprises:

lowering frequency at which said computer processor is operated prior to lowering voltage at which said computer processor is operated.

41. The method of claim 40, wherein said dynamically changing power consumption further comprises:

increasing voltage at which said computer processor is operated prior to increasing frequency at which said computer processor is operated.

42. The method of claim 40, wherein said implementing further comprises:

executing instructions in said computer processor while lowering voltage at which said computer processor is operated.

43. The method of claim 39, wherein said dynamically changing power consumption comprises:

increasing voltage at which said computer processor is operated prior to increasing frequency at which said computer processor is operated.

44. The method of claim 39, wherein said monitoring comprises monitoring a state of said computer processor.

45. The method of claim 44, wherein said state comprises a halt state.

46. The method of claim 44, wherein said state comprises a sleep state.

47. The method of claim 46, wherein said monitoring further comprises monitoring a halt state of said computer processor.

48. The method of claim 39, wherein said monitoring comprises monitoring a temperature.

49. The method of claim 48, wherein said monitoring further comprises monitoring a state of said computer processor.

50. The method of claim 49, wherein said state comprises a halt state.

51. The method of claim 49, wherein said state comprises a sleep state.

52. The method of claim 51, wherein said monitoring further comprises monitoring a halt state of said computer processor.

53. The method of claim 48, wherein said dynamically changing the power consumption comprises lowering frequency prior to lowering voltage.

54. The method of claim 39, wherein said determining a voltage-frequency pair comprises accessing a table of pre-determined voltage-frequency pairs.

55. The method of claim 39, wherein said determining a voltage-frequency pair comprises calculating a voltage-frequency pair.

56. A computing device comprising:

a power supply furnishing selectable output voltages;

a clock frequency source; and

a central processor comprising;

a clock frequency generator receiving a clock frequency from the clock frequency source; and

a processing unit operable to provide values indicative of operating conditions of the central processor and to cause the power supply and the clock frequency generator to furnish a voltage level and an output clock frequency for the central processor, wherein said processing unit is further operable to cause the power supply to cause voltage furnished to the central processor to change while the central processor is executing instructions.

57. The computing device of claim 56, wherein:

said clock frequency generator is operable to provide one of a plurality of selectable output clock frequencies to the processing unit.

58. The computing device of claim 57, wherein:

said clock frequency generator is further operable to concurrently generate frequencies for a plurality of functional units of the computing device.

59. The computing device of claim 56, wherein:

said clock frequency generator is operable to concurrently generate frequencies for a plurality of functional units of the computing device.