System and method for allocating fail-over memory

• US 7,100,071 B2
• Filed: 07/31/2002
• Issued: 08/29/2006
• Est. Priority Date: 07/16/1998
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Olarig, Sompong P.
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): MCCARTHY, CHRISTOPHER S
• Application Number:
  US10/210,553
• Publication Number:
  US 20030037278A1
• Time in Patent Office: 1,490 Days
• Field of Search: 714/5, 714/8, 714/7, 714/6, 711/6, 711/203
• US Class Current: 714/5.1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A fail-over system for memory is provided. The fail-over system for memory includes a virtual channel memory controller providing one or more virtual channel memories in a memory array. A memory fail-over controller coupled to the virtual channel memory controller provides memory fail-over data to the virtual channel memory controller. The virtual channel memory controller allocates one or more of the virtual channel memories to one or more fail-over memory channels in response to the memory fail-over data.

Claims

1. A fail-over system comprising:

a virtual channel memory controller providing virtual channel memories in a memory array having memory blocks, the virtual channel memories associated with respective memory blocks;

a memory fail-over controller coupled to the virtual channel memory controller, the memory fail-over controller to detect memory failure in a first segment of one of the memory blocks, the one memory block also having a second segment that has not exhibited failure; and

wherein the virtual channel memory controller allocates one or more of the virtual channel memories as one or more fail-over memories in response to detection of the memory failure, the one or more fail-over memories to store data in the first segment, and

wherein the virtual channel memory controller allocates another of the virtual channel memories to the second segment of the one memory block.

2. The fail-over system of claim 1 wherein the memory fail-over controller further comprises a fail-over status system generating status data that indicates the virtual channel memories that are being used as fail-over memories.

3. The fail-over system of claim 1 wherein the memory fail-over controller further comprises a memory remapping system generating fail-over memory channel address data that corresponds to one or more failed memory locations in the memory array.

4. The fail-over system of claim 1 wherein the memory fail-over controller further comprises an error indication system generating error indication data in response to detection of memory failure.

5. The fail-over system of claim 3, wherein the memory fail-over controller further comprises a memory stall system stalling access to the fail-over memories during remapping.

6. The fail-over system of claim 5 wherein the memory stall system implements a prefetch command.

7. The fail-over system of claim 1 wherein the memory fail-over controller further comprises a virtual channel memory controller interface.

8. The fail-over system of claim 1 wherein the virtual channel memory controller further comprises a replacement system with fail-over detect.

9. The fail-over system of claim 1 wherein the virtual channel memory controller further comprises a write system with fail-over detect.

10. A method for providing a fail-over memory comprising:

associating plural memory blocks with respective virtual channel memories;

detecting a memory failure condition in a first segment of one of the memory blocks, the one memory block having a second segment not exhibiting failure;

redesignating one or more of the virtual channel memories as a fail-over memory to store data of the first segment of the one memory block; and

reallocating another one of the virtual channel memories to the second segment of the one memory block.

11. The method of claim 10 wherein detecting a memory failure condition comprises detecting an incipient failure.

12. The method of claim 11 further comprising transferring data stored in the first segment to the fail-over memory.

13. The method of claim 12 further comprising stalling requests to the first segment while transferring the data stored in the first segment to the fail-over memory.

14. The method of claim 10 wherein detecting a memory failure condition comprises detecting excessive ECC error codes.

15. The method of claim 10 wherein detecting a memory failure condition comprises detecting a catastrophic failure.

16. The method of claim 10 further comprising generating a notification that the one or more virtual channel memories is operating as a fail-over memory.

17. The method of claim 10, further comprising generating status data to indicate that the first virtual channel memory has changed state from the virtual channel memory to the fail-over memory.

18. A system comprising:

a memory array containing plural memory blocks;

a plurality of virtual channels to control respective memory blocks, the virtual channels providing virtual channel memories;

a fail-over module to detect a defective portion of a first one of the memory blocks, the first one of the memory blocks also having a second portion that is not defective; and

a controller to change a state of a first one of the virtual channel memories to a fail-over memory, the fail-over memory to store data from the defective portion of the first memory block, and

the controller to change a state of a second one of the virtual channel memories to be associated with the second portion of the first memory block.

19. The system of claim 18, the fail-over module to transfer data from the defective portion of the first memory block to the fail-over memory.

20. The system of claim 19, the fail-over module to remap addressing of data in the defective portion to the fail-over memory.

21. The system of claim 18, the fail-over module to generate a status indication to indicate that the first virtual channel memory has been changed from a virtual channel memory to a fail-over memory.