Special encoding of known bad data

• US 7,100,096 B2
• Filed: 09/30/2003
• Issued: 08/29/2006
• Est. Priority Date: 08/31/2000
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Webb, David Arthur James Jr., Kessler, Richard E., Lang, Steve
• Primary Examiner(s): Bonzo, Bryce P.
• Assistant Examiner(s): LOHN, JOSHUA A
• Application Number:
  US10/675,133
• Publication Number:
  US 20040073851A1
• Time in Patent Office: 1,064 Days
• Field of Search: 714/49, 714/52, 714/54, 714/57
• US Class Current: 714/52
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0763 by bit configuration check, e.g. of formats or tags

Abstract

A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the message contains corrupted data. The processor then replaces the corrupted portion with a predetermined bit pattern known or otherwise programmed into all other processors in the system. The predetermined bit pattern indicates that the associated portion of data was corrupted. The processor that detects the error in the message preferably alerts the system that an error has been detected. The message now containing the predetermined bit pattern in place of the corrupted data is retransmitted to another processor. The predetermined bit pattern will indicate that an error in the message was detected by the previous processor. In response, the processor detecting the predetermined bit pattern preferably will not alert the system of the existence of an error. The same message with the predetermined bit pattern can be retransmitted to other processors which also will detect the presence of the predetermined bit pattern and in response not alert the system of the presence of an error. As such, because only the first processor to detect an error alerts the system of the error and because messages containing uncorrectable errors still are transmitted through the system, fault isolation is improved and the system is less likely to fall into a deadlock condition.

Claims

1. A computer system, comprising:

a plurality of processors coupled together between which messages can be routed;

an I/O controller coupled to one or more of said processors;

at least one I/O device coupled to an I/O controller; and

wherein each processor is capable of detecting an error in a message sent from another processor in the system and reformatting the message to indicate to other of said processors that the message contains a transmission error;

wherein each of said messages between said processors comprises a header ticks and data tick, the data tick comprising error check bits, and wherein upon detecting an error has occurred in the message, the processor alters the data tick error check bits in a predetermined manner to indicate to other of said processors that the message contains an error.

2. A computer system, comprising:

a plurality of processors coupled together between which messages can be routed;

an I/O controller coupled to one or more of said processors;

at least one I/O device coupled to an I/O controller;

wherein each processor is capable of detecting an error in a message sent from another processor in the system and reformatting the message to indicate to other of said processors that the message contains a transmission error;

wherein each of said messages between said processors comprises a header tick and a data tick, each tick comprising multiple bits of information, and wherein upon detecting an error has occurred in a data tick, the processor replaces the bits of information in the data tick with a predetermined bit pattern.

3. The computer system of claim 2 wherein said predetermined bit pattern includes a known double bit error code.

4. A processor, comprising:

a memory controller that coordinates transactions to a memory device; and

a router coupled to said memory controller and providing interfaces to one or more other processors;

wherein said router is capable of detecting a transmission error in a message received from another processor and reformatting the message to indicate that the message contains a transmission error that has already been detected;

wherein said message comprises a data block and a block comprising error check bits, and wherein upon detecting that a transmission error has occurred in tbe message, the router alters the error check bits in a predetermined manner to indicate that the message contains a transmission error.

5. A processor, comprising:

a memory controller that coordinates transactions to a memory device; and

a router coupled to said memory controller and providing interfaces to one or more other processors;

wherein said router is capable of detecting a transmission error in a message received from another processor and reformatting the message to indicate that the message contains a transmission error that has already been detected;

wherein said message comprises a data block and a header block, and wherein upon detecting that a transmission error has occurred in the data block the router replaces the bits of information in the data block with a predetermined bit pattern.

6. The computer system of claim 5 wherein said predetermined bit pattern includes a known double bit error code.

7. A method of fault isolation in a multi-processor computer system, comprising:

(a) receiving a message;

(b) detecting an error in said message;

(c) replacing the erroneous portion of said message with a predetermined bit pattern to indicate to other processors in said system that an error has occurred in said message and said error has already been detected; and

(d) transmitting the message to another processor in said system.

8. The method of claim 7 further including:

(e) alerting the system that a fault has been detected in said message.

9. The method of claim 8 further including:

(f) receiving said message that has been altered in (c);

(g) determining whether said message includes said predetermined bit pattern; and

(h) if said message includes said predetermined bit pattern, not alerting the system that a fault is present in said message.

10. The method of claim 9 further including:

(i) transmitting said message with said predetermined bit pattern to another processor in said system.

11. The method of claim 7 further including:

(j) receiving said message that has been altered in (c);

(k) determining whether said message includes said predetermined bit pattern; and

(l) if said message includes said predetermined bit pattern, not alerting the system that a fault is present in said message.

12. The method of claim 11 further including:

(m) transmitting said message with said predetermined bit pattern to another processor in said system.