Computer system and method to dynamically generate system on a chip description files and verification information

• US 7,100,133 B1
• Filed: 06/23/2000
• Issued: 08/29/2006
• Est. Priority Date: 06/23/2000
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Vajjhala, Varaprasad, Meiyappan, Subramanian S., Petryk, Edward M.
• Primary Examiner(s): WHITMORE, STACY
• Application Number:
  US09/602,422
• Time in Patent Office: 2,258 Days
• Field of Search: 716/4, 716/5, 716/17, 716/18
• US Class Current: 716/102
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

The present invention facilitates automation of system on a chip (SoC) design, manufacture and verification in a convenient and efficient manner. In one embodiment, a SoC netlist builder and verification computer system of the present invention includes a user interface module, a parameter application module, an expert system module and a chip level netlist generation module. The user interface module provides user friendly and convenient interfaces that facilitate easy entry and modification of user selections and parameters. The parameter application module interprets information supplied by the user module and the expert system module and creates directions (e.g., command lines) passed to other modules for execution. The expert system module analyzes information and automatically provides SoC building and verification data including automated addition of default architectural features, automated insertion of default parameters, and automated input of information to the verification module. The chip level netlist generation module automatically generates a chip level netlist, including the instantiation of internal IC devices and connections between the circuit blocks for internal signals. The verification module automatically generates a test bench and a logical verification environment including simulation models (e.g., a chip model and a system level model).

Claims

1. A System on a Chip (SoC) netlist builder and verification computer system comprising:

a user interface module for providing user friendly and convenient interfaces that facilitate easy entry and modification of user selections and parameters;

an expert system module for analyzing information supplied by said user module and automatically providing SoC building and verification data to a parameter application module;

a parameter application module for applying parameters and developing command line strings based upon information received from said user interface and said expert system;

a chip level netlist generation module for automatically generating a chip level netlist based upon information received from said user interface module and said expert system module; and

a verification module for generating a test bench and a logical verification environment automatically including simulation models based upon information interpreted by said parameter application module.

2. The System on a Chip (SoC) netlist builder and verification computer system of claim 1 wherein said parameter application module creates directions passed to other modules for execution.

3. The System on a Chip (SoC) netlist builder and verification computer system of claim 2 wherein said directions passed to other modules for execution includes command lines.

4. The System on a Chip (SoC)_netlist builder and verification computer system of claim 1 wherein said SoC building and verification data provided by said expert system is retrieved from a storage medium comprising a database of building block circuit description files.

5. The System on a Chip (SoC) netlist builder and verification computer system of claim 1 wherein said chip level netlist generation module includes the instantiation of internal integrated circuit (IC) devices and connections between the IC devices for internal signals.

6. The System on a Chip (SoC) netlist builder and verification computer system of claim 1 wherein said user interface module generates user friendly graphical user interfaces (GUIs) to facilitate selection of standardized circuit blocks and parameterization of the selected standardized circuit blocks.

7. In a computer system, a system on a chip netlist builder and verification computer method for facilitating creation and modification of internal integrated circuit (IC) designs utilizing existing circuit block designs, said method comprising the steps of:

providing a user friendly interface;

performing a parameter application process;

executing an expert system process;

implementing a chip level netlist generation process including core netlist and I/O pin netlists;

verifying a system on a chip design automatically;

creating an underlying structure list, wherein creating the underlying structure list comprises,

interpreting information and commands entred by a user; and

performing required iterations.

8. The system on a chip netlist builder and verification computer method of claim 7 further comprising the steps of:

assisting easy entry and modification of user selections and parameters;

presenting information regarding operations of said SoC netlist builder and verification method to a user; and

facilitating selection of standardized circuit blocks and parameterization of said selected standardized circuit blocks.

9. The system on a chip netlist builder and verification computer method of claim 8 further comprising the steps of:

determining which circuit block is selected by a user;

initializing a parameterizable command line string;

processing operations for the circuit block a user has requested;

making an instance specific copy of the parameterizable command line string; and

updating a copy of the parameterizable command line string with user indicated parameters received for a particular instance.

10. The system on a chip netlist builder and verification computer method of claim 8 further comprising the steps of:

appending the circuit block attributes to other files; and

adding the gate count of a circuit block to a list of gate counts for an IC.

11. The system on a chip netlist builder and verification computer method of claim 8 further comprising the steps of:

generating an internal integration list associated with the circuit block designs; and

utilizing said internal integration list in the processing of other routines included in the SoC netlist building and verification computer method.

12. The system on a chip netlist builder and verification computer method of claim 8 further comprising the step of extracting circuit block descriptions from a storage location based upon the applied parameter information.

13. The system on a chip netlist builder and verification computer method of claim 8 further comprising the steps of:

creating an internal integrated circuit (IC) core level netlist in a desired location based on data

structures that were populated in other routines of said SoC netlist builder and verification computer method; and

generating hardware description language VHDL or Verilog code that automatically performs the task of coupling circuit blocks together.

14. The system on a chip netlist builder and verification computer method of claim 8 further comprising the steps of:

providing signal declarations;

producing required HDL assign statements in accordance with an assignment list; and

generating the HDL code that will instantiate the signal declarations and HDL assign statements_based upon an instantiation list.