Method and apparatus for quantifying the quality of placement configurations in a partitioned region of an integrated circuit layout

• US 7,100,137 B2
• Filed: 12/19/2000
• Issued: 08/29/2006
• Est. Priority Date: 12/06/2000
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Teig, Steven, Ganley, Joseph L.
• Primary Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/742,171
• Publication Number:
  US 20030217346A1
• Time in Patent Office: 2,079 Days
• Field of Search: 716/7, 716/9, 716/10
• US Class Current: 716/123
• CPC Class Codes: G06F 2111/06 Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G11B 7/08582 Sled-type positioners

Abstract

One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net'"'"'s configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net'"'"'s configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net'"'"'s circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.

Claims

1. For an electronic-design-automation placer that uses a set of partitioning lines, that define a plurality of slots, to partition an integrated-circuit (“

IC”

) layout region into a plurality of sub-regions corresponding to said slots, wherein a plurality of line paths exist between said slots, a method of pre-computing attributes that are used for placing circuit modules in an IC layout region, the method comprising;

a) for each combination of said slots, identifying at least one connection graph that represents a topology of interconnect lines necessary for connecting the combination of said slots;

b) for each combination of said slots, identifying the line paths used by the at least one connection graph for that particular combination of slots, wherein a plurality of the identified line paths are diagonal; and

c) storing the plurality of identified line paths for each combination of slots in a storage structure, wherein said stored line paths are used by the placer to compute costs associated with different placements of said circuit modules.

2. The method of claim 1, wherein a plurality of the line paths are horizontal, and a plurality are vertical.

3. The method of claim 1, wherein the at least one connection graph is a Steiner tree.

4. The method of claim 1, wherein the at least one connection is a minimum spanning tree.

5. The method of claim 1, wherein the at least one connection graph is determined to be optimal based on at least one particular selection criterion.

6. The method of claim 5, wherein identifying the line paths comprises identifying the line paths used by all optimal connection graphs for each combination of said slots.

7. The method of claim 1, wherein the at least one particular selection criterion is the length of the at least one connection graph.

8. The method of claim 7, wherein another selection criterion for determining whether the at least one connection graph is optimal is the number of bends of the at least one connection graph.

9. The method of claim 1, wherein the line paths are defined based on a wiring model for the IC layout and on a partitioning structure defined by the partitioning lines.

10. For an electronic-design-automation placer that uses a set of partitioning lines, that define a plurality of slots, to partition an integrated-circuit (“

IC”

) layout region into a plurality of sub-regions corresponding to said slots, wherein a plurality of edges exist between said slots, a method of pre-computing attributes that are used for placing circuit modules in an IC layout region, the method comprising;

a) for each combination of said slots, identifying at least one connection graph that represents a topology of interconnect lines necessary for connecting the combination of said slots;

b) for each combination of said slots, identifying the edges intersected by the at least one connection graph for that particular combination of slots, wherein a plurality of the identified edges are diagonal; and

c) storing the plurality of identified edges for each combination of slots in a storage structure, wherein said stored edges are used by the placer to compute costs associated with different placements of said circuit modules.

11. The method of claim 10, wherein a plurality of the edges are horizontal, and a plurality are vertical.

12. The method of claim 10, wherein the at least one connection graph is a Steiner tree.

13. The method of claim 10, wherein the at least one connection graph is a minimum spanning tree.

14. The method of claim 10, wherein the at least one connection graph is determined to be optimal based on at least one particular selection criterion.

15. The method of claim 14, wherein identifying the edges comprises identifying the edges intersected by all optimal connection graphs for each combination of said slots.

16. The method of claim 15, wherein the selection criterion is the length of the at least one connection graph.

17. The method of claim 16, wherein another selection criterion for determining whether the at least one connection graph is optimal, is the number of bends of the connection graph.

18. The method of claim 10, wherein the edges are defined based on a wiring model for the IC layout and on a partitioning structure defined by the partitioning lines.