Gate dielectric antifuse circuit to protect a high-voltage transistor

• US 7,101,738 B2
• Filed: 08/31/2004
• Issued: 09/05/2006
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Micron Technology, Inc.
• Inventors: Porter, John D., Marr, Kenneth W.
• Primary Examiner(s): Blum, David S.
• Application Number:
  US10/931,366
• Publication Number:
  US 20050029598A1
• Time in Patent Office: 735 Days
• Field of Search: 365/189.01, 365/189.05, 365/189.09, 438/131
• US Class Current: 438/131
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.

Claims

1. A method of operating an antifuse circuit comprising:

coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit during a programming mode of operation, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;

bearing a portion of the elevated voltage on a high-voltage transistor coupled to the second terminal of the antifuse during the programming mode;

coupling a first intermediate voltage between the elevated voltage and a supply voltage to a gate terminal of the high-voltage transistor to protect the high-voltage transistor during the programming mode;

coupling a read voltage to the first terminal of the antifuse during an active mode of operation when the antifuse is being read; and

coupling a second intermediate voltage between the read voltage and the supply voltage to the gate terminal of the high-voltage transistor during the active mode.

2. The method of claim 1 wherein:

coupling an elevated voltage further comprises coupling the elevated voltage to a gate electrode of the antifuse during the programming mode, the antifuse comprising a layer of gate dielectric between the gate electrode and a well in a substrate;

coupling a read voltage further comprises coupling the supply voltage to the first terminal of the antifuse during the active mode; and

coupling a second intermediate voltage further comprises coupling approximately the supply voltage to the gate terminal of the high-voltage transistor during the active mode.

3. The method of claim 1 wherein bearing a portion of the elevated voltage further comprises bearing a portion of the elevated voltage on a drain of the high-voltage transistor coupled to the well of the antifuse during the programming mode, the high-voltage transistor comprising:

an n-type well in a p-type substrate;

an n+-type drain diffusion region in the well comprising the drain;

an n+-type source diffusion region in the substrate comprising a source;

a layer of oxide over the substrate; and

a gate electrode over the layer of oxide.

4. The method of claim 1, further comprising:

generating the first intermediate voltage and the second intermediate voltage in a gate bias circuit comprising a first impedance coupled between the first terminal of the antifuse and the gate terminal of the high-voltage transistor and a second impedance coupled between the gate terminal of the high-voltage transistor and the supply voltage;

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor; and

reading the antifuse with a read circuit coupled to the high-voltage transistor during the active mode.

5. A method of operating an antifuse circuit comprising:

coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit during a programming mode of operation, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;

bearing a portion of the elevated voltage on a high-voltage transistor coupled to the second terminal of the antifuse during the programming mode;

generating a first intermediate voltage at a gate terminal of the high-voltage transistor coupled to a first impedance and a second impedance, the first intermediate voltage being between the elevated voltage and a supply voltage during the programming mode to protect the high-voltage transistor, the first impedance being coupled between the first terminal of the antifuse and the gate terminal of the high-voltage transistor, and the second impedance being coupled between the supply voltage and the gate terminal of the high-voltage transistor;

coupling a read voltage to the first terminal of the antifuse during an active mode of operation when the antifuse is being read; and

generating a second intermediate voltage at the gate terminal of the high-voltage transistor during the active mode to be between the read voltage and the supply voltage.

6. The method of claim 5 wherein:

coupling an elevated voltage further comprises coupling the elevated voltage to a common bus line coupled to a gate electrode of the antifuse during the programming mode, the antifuse comprising a layer of gate dielectric between the gate electrode and a well in a substrate;

coupling a read voltage further comprises coupling the supply voltage to the common bus line during the active mode;

generating a second intermediate voltage further comprises generating the second intermediate voltage to be approximately equal to the supply voltage; and

generating a first intermediate voltage further comprises generating the first intermediate voltage at the gate terminal of the high-voltage transistor, the first impedance comprising a transistor and a first adjustable resistor coupled in series, and the second impedance comprising a second adjustable resistor.

7. The method of claim 5 wherein bearing a portion of the elevated voltage further comprises bearing a portion of the elevated voltage on a drain of the high-voltage transistor coupled to the well of the antifuse during the programming mode, the high-voltage transistor comprising:

an n-type well in a p-type substrate;

an n+-type drain diffusion region in the well comprising the drain;

an n+-type source diffusion region in the substrate comprising a source;

a layer of oxide over the substrate; and

a gate electrode over the layer of oxide.

8. The method of claim 5, further comprising:

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor; and

reading the antifuse with a read circuit coupled to the high-voltage transistor during the active mode.

9. A method of operating an integrated circuit comprising:

coupling an elevated voltage to a common bus line in an integrated circuit to program an antifuse in the integrated circuit during a programming mode of operation;

selecting a first antifuse in the integrated circuit to be programmed, the first antifuse being coupled to the common bus line;

bearing a portion of the elevated voltage on a second antifuse having a first terminal coupled to the common bus line in the integrated circuit, the second antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;

bearing a portion of the elevated voltage on a high-voltage transistor coupled to the second terminal of the second antifuse during the programming mode;

coupling a first intermediate voltage between the elevated voltage and a supply voltage to a gate terminal of the high-voltage transistor to protect the high-voltage transistor during the programming mode;

coupling a read voltage to the common bus line during an active mode of operation when the second antifuse is being read; and

coupling a second intermediate voltage between the read voltage and the supply voltage to the gate terminal of the high-voltage transistor during the active mode.

10. The method of claim 9 wherein:

selecting a first antifuse further comprises selecting the second antifuse from a plurality of antifuses coupled to the common bus line, the second antifuse comprising a layer of gate dielectric between a gate electrode and a well in a substrate;

coupling an elevated voltage further comprises coupling a very high positive voltage to an external pin coupled to the common bus line that is coupled to the gate electrode of the second antifuse during the programming mode;

coupling a read voltage further comprises coupling the supply voltage to the common bus line during the active mode; and

coupling a second intermediate voltage further comprises coupling approximately the supply voltage to the gate terminal of the high-voltage transistor during the active mode.

11. The method of claim 9 wherein bearing a portion of the elevated voltage on a high-voltage transistor further comprises bearing a portion of the elevated voltage on a drain of the high-voltage transistor coupled to the well of the second antifuse during the programming mode, the high-voltage transistor comprising:

an n-type well in a p-type substrate;

an n+-type drain diffusion region in the well comprising the drain;

an n+-type source diffusion region in the substrate comprising a source;

a layer of oxide over the substrate; and

a gate electrode over the layer of oxide.

12. The method of claim 9, further comprising:

generating the first intermediate voltage and the second intermediate voltage in a gate bias circuit comprising a first impedance coupled between the common bus line and the gate terminal of the high-voltage transistor and a second impedance coupled between the gate terminal of the high-voltage transistor and the supply voltage;

controlling current flowing through the second antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor; and

reading the second antifuse with a read circuit coupled to the high-voltage transistor during the active mode.

13. A method of operating a memory device comprising:

accessing memory cells in an array of memory cells in a memory device by decoding address signals in an address decoder coupled to the array in the memory device;

coupling data to the memory cells through a plurality of input/output paths coupled to the array;

controlling the data on the input/output paths with an input/output control circuit;

coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit in the memory device during a programming mode of operation, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;

bearing a portion of the elevated voltage on a high-voltage transistor coupled to the second terminal of the antifuse during the programming mode;

coupling a first intermediate voltage between the elevated voltage and a supply voltage to a gate terminal of the high-voltage transistor to protect the high-voltage transistor during the programming mode;

coupling a read voltage to the first terminal of the antifuse during an active mode of operation when the antifuse is being read; and

coupling a second intermediate voltage between the read voltage and the supply voltage to the gate terminal of the high-voltage transistor during the active mode.

14. The method of claim 13 wherein:

coupling an elevated voltage further comprises coupling the elevated voltage to a gate electrode of the antifuse during the programming mode, the antifuse comprising a layer of gate dielectric between the gate electrode and a well in a substrate;

coupling a read voltage further comprises coupling the supply voltage to the first terminal of the antifuse during the active mode; and

coupling a second intermediate voltage further comprises coupling approximately the supply voltage to the gate terminal of the high-voltage transistor during the active mode.

15. The method of claim 13 wherein bearing a portion of the elevated voltage further comprises bearing a portion of the elevated voltage on a drain of the high-voltage transistor coupled to the well of the antifuse during the programming mode, the high-voltage transistor comprising:

an n-type well in a p-type substrate;

an n+-type drain diffusion region in the well comprising the drain;

an n+-type source diffusion region in the substrate comprising a source;

a layer of oxide over the substrate; and

a gate electrode over the layer of oxide.

16. The method of claim 13, further comprising:

generating the first intermediate voltage and the second intermediate voltage in a gate bias circuit comprising a first impedance coupled between the first terminal of the antifuse and the gate terminal of the high-voltage transistor and a second impedance coupled between the gate terminal of the high-voltage transistor and the supply voltage;

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor; and

reading the antifuse with a read circuit coupled to the high-voltage transistor during the active mode.

17. The method of claim 13 wherein accessing memory cells further comprises accessing memory cells in an array of memory cells in a static random access memory device.

18. The method of claim 13 wherein:

controlling the data further comprises controlling the data on the input/output paths in response to a write enable signal, an output enable signal, and a chip enable signal coupled to the input/output control circuit; and

further comprising controlling the memory device with a power down circuit in the memory device coupled to the array during a power-down mode.

19. A method of operating a system comprising:

exchanging signals between a processor and a memory system coupled together;

coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit in the memory system during a programming mode of operation, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;

bearing a portion of the elevated voltage on a high-voltage transistor coupled to the second terminal of the antifuse during the programming mode;

coupling a first intermediate voltage between the elevated voltage and a supply voltage to a gate terminal of the high-voltage transistor to protect the high-voltage transistor during the programming mode;

coupling a read voltage to the first terminal of the antifuse during an active mode of operation when the antifuse is being read; and

coupling a second intermediate voltage between the read voltage and the supply voltage to the gate terminal of the high-voltage transistor during the active mode.

20. The method of claim 19 wherein:

coupling an elevated voltage further comprises coupling the elevated voltage to a gate electrode of the antifuse during the programming mode, the antifuse comprising a layer of gate dielectric between the gate electrode and a well in a substrate;

coupling a read voltage further comprises coupling the supply voltage to the first terminal of the antifuse during the active mode; and

coupling a second intermediate voltage further comprises coupling approximately the supply voltage to the gate terminal of the high-voltage transistor during the active mode.

21. The method of claim 19 wherein bearing a portion of the elevated voltage further comprises bearing a portion of the elevated voltage on a drain of the high-voltage transistor coupled to the well of the antifuse during the programming mode, the high-voltage transistor comprising:

an n-type well in a p-type substrate;

an n+-type drain diffusion region in the well comprising the drain;

an n+-type source diffusion region in the substrate comprising a source;

a layer of oxide over the substrate; and

a gate electrode over the layer of oxide.

22. The method of claim 19, further comprising:

generating the first intermediate voltage and the second intermediate voltage in a gate bias circuit comprising a first impedance coupled between the first terminal of the antifuse and the gate terminal of the high-voltage transistor and a second impedance coupled between the gate terminal of the high-voltage transistor and the supply voltage;

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor; and

reading the antifuse with a read circuit coupled to the high-voltage transistor during the active mode.

23. The method of claim 19 wherein exchanging signals further comprises exchanging signals between the processor, the memory system, an input/output subsystem, and a display unit over a bus coupled between the processor, the memory system, the input/output subsystem, and the display unit.

24. The method of claim 19 wherein exchanging signals comprises exchanging signals between a microprocessor and a memory system coupled together.