Testing apparatus and method for thin film transistor display array

• US 7,102,378 B2
• Filed: 11/19/2003
• Issued: 09/05/2006
• Est. Priority Date: 07/29/2003
• Status: Expired due to Fees

• Current Assignee: Primetech International Corporation
• Original Assignee: Primetech International Corporation
• Inventors: Tien, Hsiao Tung, Kuo, Kuang I
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US10/717,725
• Publication Number:
  US 20050024081A1
• Time in Patent Office: 1,021 Days
• Field of Search: 324678-679, 324/684, 324769-770, 324/158.1
• US Class Current: 324/756.07
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309

Abstract

A testing circuit and method for thin film transistor display array, for testing the yield of a thin film transistor array is provided. The testing circuit includes an array tester, a test panel (DUT) and a sense amplifier array. The sense amplifier is composed of a plurality of trans-impedance amplifier units and a plurality of parasitic capacitance discharge circuit units. Every sense amplifier includes a trans-impedance amplifier, which is implemented by an operational amplifier, two switches and an operation capacitance. The trans-impedance amplifier is used to form an integrated circuit and the output is transmitted to a sampling/hold circuit via a switch. Also included is a parasitic capacitance discharge circuit that is used to form a discharge route for the charge of the parasitic capacitance.

Claims

1. A testing circuit for thin film transistor display array testing, use to test the yield of thin film transistor display array, comprising:

An array tester, providing electrical power, testing signal wave-form, for analyzing, calculating, storing testing results;

A device under test (DUT) platform, for holding the thin film transistor display array, and providing control signal to the platform and a sense amplifier by the array tester;

A sense amplifier array, for transferring (discharge) the parasitic capacitance of the source line of the thin film transistors and integrating charge current of a pixel storage capacitor;

wherein said sense amplifier array is composed by a plurality of trans-impedance amplifier units and a plurality of parasitic capacitance discharge circuits, the sense amplifier array including;

A trans-impedance amplifier, is composed by a first operational amplifier, first switch, a second switch and a first operation capacitor;

said first operation capacitor feed back the output of the first operational amplifier to the negative input of the first operational amplifier;

the first switch connecting to the output and negative input of the first operational amplifier, to short circuit the first operation capacitor for discharge;

the second switch to be the input switch, to connect or disconnect with the pixel storage capacitor;

said trans-impedance amplifier forms an integrated circuit, the output of the first operational amplifier is transmitted to a sampling/hold circuit via an output switch and converted to a digital signal;

A discharge circuit for the parasitic capacitance of the source line of the thin film transistors, composed by a second operational amplifier, third switch, a fourth switch and a second operation capacitor;

said second operation capacitor feed back the output of the second operational amplifier to the negative input of the second operational amplifier;

the third switch connecting to the output and negative input of the second operational amplifier, to short circuit the second operation capacitor for discharge;

the fourth switch to be the input switch, to connect or disconnect with the parasitic capacitance of the source line of the thin film transistors;

a load resistance connecting the output of the second operational amplifier to the ground;

said discharge circuit forms a discharge route for the parasitic capacitance.

2. A testing circuit as recited in claim 1, wherein said thin film transistor display array is liquid crystal display (LCD) panel.

3. A testing circuit as recited in claim 1, wherein said thin film transistor display array is organic light emitting diode display (OLED) panel.

4. A testing circuit as recited in claim 1, wherein said thin film transistor display array is LCOS (liquid crystal on silicon) panel.

5. A testing circuit as recited in claim 1, wherein said thin film transistor display array is formed by amorphous thin film transistors.

6. A testing circuit as recited in claim 1, wherein said thin film transistor display array is formed by poly-Si thin film transistor.

7. A testing circuit as recited in claim 1, wherein said thin film transistor display array is formed by re-crystallized silicon thin film transistor.

8. A testing circuit as recited in claim 1, wherein said amplifier is an operational amplifier.

9. A testing circuit as recited in claim 1, where in said first second, third and fourth switches are control by the programmable output waveform of said array tester.

10. A testing circuit as recited in claim 1, wherein the capacitance of said operation capacitor of said trans-impedance amplifier is 1 pf to 100 pf.

11. A testing circuit as recited in claim 1, wherein the capacitance of said operation capacitor of said discharge circuit is greater than 10 pf.

12. A testing method for invalid pixel (invisible area) of thin film transistor display array, comprising the steps of:

Charging the pixel storage capacitors of nth column of the thin film transistor display array through a pixel switch transistors to a charge voltage of V_s, then open circuit the pixel switch transistors after charging;

Switching ON short circuit switches of sense amplifiers and discharge circuits to discharge the operation capacitors of the sense amplifiers and the discharge circuits;

Switching ON input switches of the discharge circuits;

switching OFF short circuit switches to discharge the parasitic capacitance of the thin film transistor display array (transferring the charge);

Switching ON input switches of the sense amplifiers to start operation of the sense amplifiers, integrating any current from a pixel storage capacitor of column n and row k, but do not output the result of the integrated current;

Testing a next pixel (column n and row (k+1)).

14. A testing method as recited in claim 12 or 13, wherein said charging voltage V_s of the pixel capacitors is 2 Volts to 10 Volts.

13. A testing method for valid pixel (visible area) of thin film transistor display array, comprising the steps of:

Charging the pixel storage capacitors of nth column of the thin film transistor display array through a pixel switch transistors to a charge voltage of V_s, then open circuit the pixel switch transistors after charging;

Switching ON short circuit switches of sense amplifiers and discharge circuits to discharge the operation capacitors of the sense amplifiers and the discharge circuits;

Switching ON the input switches of sense amplifiers to start operation of the sense amplifier, integrating any current from a pixel storage capacitor of column n and row k, to integrate a voltage Vd;

Switching ON the input switches of discharge circuits;

switching OFF the short circuit switch of discharge circuits to discharge the parasitic capacitance of the thin film transistor display array (transferring the charge), for testing of a next pixel,

Testing the next pixel (column n and row (k+1)).

15. A testing method as recited in claim 13, wherein said integrated voltage V_d is greater than 100 mV.