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Testing apparatus and method for thin film transistor display array

  • US 7,102,378 B2
  • Filed: 11/19/2003
  • Issued: 09/05/2006
  • Est. Priority Date: 07/29/2003
  • Status: Expired due to Fees
First Claim
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1. A testing circuit for thin film transistor display array testing, use to test the yield of thin film transistor display array, comprising:

  • An array tester, providing electrical power, testing signal wave-form, for analyzing, calculating, storing testing results;

    A device under test (DUT) platform, for holding the thin film transistor display array, and providing control signal to the platform and a sense amplifier by the array tester;

    A sense amplifier array, for transferring (discharge) the parasitic capacitance of the source line of the thin film transistors and integrating charge current of a pixel storage capacitor;

    wherein said sense amplifier array is composed by a plurality of trans-impedance amplifier units and a plurality of parasitic capacitance discharge circuits, the sense amplifier array including;

    A trans-impedance amplifier, is composed by a first operational amplifier, first switch, a second switch and a first operation capacitor;

    said first operation capacitor feed back the output of the first operational amplifier to the negative input of the first operational amplifier;

    the first switch connecting to the output and negative input of the first operational amplifier, to short circuit the first operation capacitor for discharge;

    the second switch to be the input switch, to connect or disconnect with the pixel storage capacitor;

    said trans-impedance amplifier forms an integrated circuit, the output of the first operational amplifier is transmitted to a sampling/hold circuit via an output switch and converted to a digital signal;

    A discharge circuit for the parasitic capacitance of the source line of the thin film transistors, composed by a second operational amplifier, third switch, a fourth switch and a second operation capacitor;

    said second operation capacitor feed back the output of the second operational amplifier to the negative input of the second operational amplifier;

    the third switch connecting to the output and negative input of the second operational amplifier, to short circuit the second operation capacitor for discharge;

    the fourth switch to be the input switch, to connect or disconnect with the parasitic capacitance of the source line of the thin film transistors;

    a load resistance connecting the output of the second operational amplifier to the ground;

    said discharge circuit forms a discharge route for the parasitic capacitance.

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