Loading circuit capable of canceling DC offset and mixer using the same

• US 7,102,412 B2
• Filed: 02/01/2005
• Issued: 09/05/2006
• Est. Priority Date: 12/06/2004
• Status: Expired due to Fees

• Current Assignee: Sunplus Technology Co., Ltd
• Original Assignee: Sunplus Technology Co., Ltd
• Inventors: Chung, Yuan-Hung
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US11/046,772
• Publication Number:
  US 20060119413A1
• Time in Patent Office: 581 Days
• Field of Search: 327/359, 327/355
• US Class Current: 327/359
• CPC Class Codes: H03D 2200/0033 Current mirrors
• CPC Class Codes: H03D 2200/0047 Offset of DC voltage or frequency
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1458 Double balanced arrangements, i.e. where both input signals are differential

Abstract

A loading circuit capable of canceling a DC offset and a mixer using the same. The loading circuit includes a first current mirror unit and a second current mirror unit for respectively receiving a first input signal and a second input signal and generating a first signal current and a second signal current proportional to the first and second input signals, a first compensation unit and a second compensation unit for respectively receiving the first and second input signals, filtering AC components of the input signals, and generating a first compensation current and a second compensation current proportional to the DC components of the first and second input signals, a first loading unit for receiving the first signal current and the second compensation current and generating a first output signal, and a second loading unit for receiving the second signal current and the first compensation current and generating a second output signal.

Claims

1. A loading circuit capable of canceling a DC offset, the loading circuit receiving a first input signal and a second input signal and generating a first output signal and a second output signal without the DC offset and comprising:

a first current mirror unit for receiving the first input signal and generating a first signal current proportional to the first input signal;

a first compensation unit for receiving the first input signal, filtering AC components of the first input signal, and generating a first compensation current proportional to DC components of the first input signal;

a second current mirror unit for receiving the second input signal and generating a second signal current proportional to the second input signal;

a second compensation unit for receiving the second input signal, filtering AC components of the second input signal, and generating a second compensation current proportional to DC components of the second input signal;

a first loading unit for receiving the first signal current as well as the second compensation current and generating the first output signal; and

a second loading unit for receiving the second signal current as well as the first compensation current and generating the second output signal.

2. The loading circuit according to claim 1, wherein the first current mirror unit comprises:

a first transistor having a source connected to a voltage source, a drain connected to the first input signal, and a gate connected to the drain; and

a third transistor having a source connected to the voltage source, a gate connected to the first input signal, and a drain for generating the first signal current.

3. The loading circuit according to claim 2, wherein the second current mirror unit comprises:

a second transistor having a source connected to the voltage source, a drain connected to the second input signal, and a gate connected to the drain; and

a fourth transistor having a source connected to the voltage source, a gate connected to the second input signal, and a drain for generating the second signal current.

4. The loading circuit according to claim 3, wherein the first compensation unit comprises:

a first low pass filter for receiving the first input signal and generating a first filtering signal; and

a fifth transistor having a source connected to the voltage source, a gate for receiving the first filtering signal, and a drain for generating the first compensation current.

5. The loading circuit according to claim 4, wherein the second compensation unit comprises:

a second low pass filter for receiving the first input signal and generating a second filtering signal; and

a sixth transistor having a source connected to the voltage source, a gate for receiving the second filtering signal, and a drain for generating the second compensation current.

6. The loading circuit according to claim 5, wherein the first loading unit is a resistor having a first end for receiving the first signal current and the second compensation current and generating the first output voltage, and a second end that is grounded.

7. The loading circuit according to claim 5, wherein the second loading unit is a resistor having a first end for receiving the second signal current and the first compensation current and generating the second output voltage, and a second end that is grounded.

8. The loading circuit according to claim 5, wherein the first transistor and the second transistor have the same appearance ratio.

9. The loading circuit according to claim 8, wherein the third transistor, the fourth transistor, the fifth transistor and the sixth transistor have the same appearance ratio.

10. The loading circuit according to claim 8, wherein the third transistor, the fourth transistor, the fifth transistor and the sixth transistor have the same appearance ratio, which is N times that of the first transistor.

11. The loading circuit according to claim 1, wherein the first current mirror unit comprises:

a first transistor having a source that is grounded, a drain connected to the first input signal, and a gate, which is connected to the drain and generates the first input signal; and

a third transistor having a source that is grounded, a gate connected to the first input signal, and a drain for generating the first signal current.

12. The loading circuit according to claim 11, wherein the second current mirror unit comprises:

a second transistor having a source that is grounded, a drain connected to the second input signal, and a gate, which is connected to the drain and generates the second input signal; and

a fourth transistor having a source that is grounded, a gate connected to the second input signal, and a drain for generating the second signal current.

13. The loading circuit according to claim 12, wherein the first compensation unit comprises:

a first low pass filter for receiving the first input signal and generating a first filtering signal; and

a fifth transistor having a source that is grounded, a gate for receiving the first filtering signal, and a drain for generating the first compensation current.

14. The loading circuit according to claim 13, wherein the second compensation unit comprises:

a second low pass filter for receiving the first input signal and generating a second filtering signal; and

a sixth transistor having a source that is grounded, a gate for receiving the second filtering signal, and a drain for generating the second compensation current.

15. The loading circuit according to claim 14, wherein the first loading unit is a resistor having a first end for receiving the first signal current and the second compensation current and generating the first output voltage, and a second end connected to the voltage source.

16. The loading circuit according to claim 14, wherein the second loading unit is a resistor having a first end for receiving the second signal current and the first compensation current and generating the second output voltage, and a second end connected to the voltage source.

17. The loading circuit according to claim 14, wherein the first transistor and the second transistor have the same appearance ratio.

18. The loading circuit according to claim 17, wherein the third transistor, the fourth transistor, the fifth transistor and the sixth transistor have the same appearance ratio.

19. The loading circuit according to claim 17, wherein the third transistor, the fourth transistor, the fifth transistor and the sixth transistor have the same appearance ratio, which is N times that of the first transistor.

20. The loading circuit according to claim 1 being used in a mixer.