Voltage boosting circuit and method of generating boosting voltage, capable of alleviating effects of high voltage stress

• US 7,102,423 B2
• Filed: 12/09/2003
• Issued: 09/05/2006
• Est. Priority Date: 12/10/2002
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Seung-Hoon, Sim, Jae-Yoon
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US10/732,826
• Publication Number:
  US 20040183586A1
• Time in Patent Office: 1,001 Days
• Field of Search: 327/536, 327/537, 363/59, 363/60
• US Class Current: 327/536
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A voltage boosting circuit and a method of generating a boosting voltage alleviate deterioration of a driver transistor caused by high voltage stress when the level of an external supply voltage is high. The voltage boosting circuit includes boosting capacitors and switches. The boosting capacitors include a first boosting capacitor connected to a driving node and a last boosting capacitor that outputs the boosting voltage. The switches connect the boosting capacitors in series in response to a control signal. The boosting voltage increases or decreases as the voltage level at the driving node changes according to the logic state of a boosting level control signal. The boosting level control signal is responsive to the external supply voltage level. An external supply voltage detector detects the level of external supply voltage level and generates the boosting level control signal.

Claims

1. A voltage boosting circuit comprising:

boosting capacitors that include a first boosting capacitor connected to a driving node and a last boosting capacitor configured to output a boosting voltage;

switches configured to connect the boosting capacitors in series in response to a control signal, the boosting voltage configured to vary as a voltage level at the driving node changes according to a logic state of a boosting level control signal;

a logic device having an output applied to the driving node and an input to receive the boosting level control signal, wherein the control signal and the boosting level control signal are configured to operate independently of each other, wherein the logic state of the boosting level control signal is configured to enter a logic high state or a logic low state in response to an external supply voltage level; and

an external supply voltage detector configured to detect the external supply voltage level and to generate the boosting level control signal.

2. The voltage boosting circuit of claim 1, configured such that when the boosting level control signal is in a first logic state, the voltage level at the driving node changes from a ground voltage level to an external supply voltage level, thus increasing the boosting voltage level.

3. The voltage boosting circuit of claim 2, configured such that when the boosting level control signal is in a second logic state, the voltage level at the driving node is fixed at a ground voltage level, thus decreasing the boosting voltage level.

4. The voltage boosting circuit of claim 1, wherein the driving node is configured to have a constant voltage during both an open and closed state of the switches.

5. The voltage boosting circuit of claim 3, having N boosting capacitors, wherein N is an integer greater than 1.

6. The voltage boosting circuit of claim 5, wherein the boosting level voltage is substantially equal to (N+1) multiplied by the external supply voltage level for the first logic state, and substantially equal to N multiplied by the external supply voltage level for the second logic state.

7. The voltage boosting circuit of claim 1, wherein the logic device is a NOR gate.

8. The voltage boosting circuit of claim 1, wherein the voltage level at the driving node is responsive to an input signal that is logically combined with the boosting level control signal.

9. The voltage boosting circuit of claim 1, further comprising an external supply voltage detector to detect an external supply voltage, wherein the external supply voltage detector outputs a logic signal responsive to the external supply voltage.

10. The voltage boosting circuit of claim 9, wherein the external supply voltage detector output is the boosting level control signal.

11. The voltage boosting circuit of claim 1, further comprising a transistor disposed between one side of the first boosting capacitor and an external power supply for affecting the voltage at the first boosting capacitor depending on the driving state of the transistor.

12. A method of generating a boosting voltage in a voltage boosting circuit that includes boosting capacitors with a first boosting capacitor connected to a driving node and a last boosting capacitor that outputs the boosting voltage, switches that connect the boosting capacitors in series in response to a control signal, and a logic device having an output applied to the driving node and an input to receive a boosting level control signal, the method comprising:

detecting an external supply voltage level using an external supply voltage detector;

generating the boosting level control signal as an output of the external supply voltage detector, wherein a logic state of the boosting level control signal is configured to enter a logic high state or a logic low state in response to the external supply voltage level;

increasing the boosting voltage by changing a voltage level at the driving node from a ground voltage level to the external supply voltage level when the boosting level control signal is in the logic high state; and

decreasing the boosting voltage by an amount approximately equal to the external supply voltage level by fixing the voltage level at the driving node to the ground voltage level when the boosting level control signal is in the logic low state, wherein the control signal and the boosting level control signal are configured to operate independently of each other.

13. A voltage boosting circuit, comprising:

a first boosting capacitor and a second boosting capacitor, wherein the second boosting capacitor outputs a boosted voltage;

one or more switches, which are responsive to a first control signal, to connect the first and the second boosting capacitors in series;

a pull-up transistor circuit and a pull-down transistor circuit, both pull-up and pull-down transistor circuits each having transistors that are connected to the one or more switches;

an external supply voltage detector configured to detect an external supply voltage level and to generate a second control signal, wherein a logic state of the second control signal is configured to enter a logic high state or a logic low state in response to the external supply voltage level; and

a logic device, which is responsive to the second control signal, for applying one of a plurality of voltage levels to the first boosting capacitor, wherein the second control signal and the first control signal are configured to operate independently of each other.

14. The voltage boosting circuit of claim 13, further comprising one or more additional boosting capacitors between the first and the second boosting capacitors.

15. The voltage boosting circuit of claim 14, further comprising one or more additional switches to connect the one or more additional boosting capacitors and the first and the second boosting capacitors in series in response to the first control signal.

16. The voltage boosting circuit of claim 13, further comprising a precharge control signal commonly connected to both the pull-up transistor circuit and the pull-down transistor circuit.

17. The voltage boosting circuit of claim 13, wherein the pull-up transistor circuit and the pull-down transistor circuit are both commonly responsive to a precharge control signal.

18. The voltage boosting circuit of claim 13, wherein the logic device includes a NAND gate.