Delay stage for oscillator circuit and corresponding applications

• US 7,102,449 B1
• Filed: 01/21/2003
• Issued: 09/05/2006
• Est. Priority Date: 01/21/2003
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Barcelona Design, Inc.
• Inventors: Mohan, Sunderarajan S.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Chang, Joseph
• Application Number:
  US10/348,822
• Time in Patent Office: 1,323 Days
• Field of Search: 331/57, 331/17, 327/57, 327/112
• US Class Current: 331/57
• CPC Class Codes: H03K 2005/00208 using differential stages
• CPC Class Codes: H03K 3/0322 with differential cells

Abstract

An oscillator delay stage is described. The oscillator delay stage includes at least one differential input; a pair of single ended inverters for each differential input; and, a differential output. With respect to the pair of single ended inverters for each differential input, each pair of single ended inverters further include for their corresponding differential input: i) a first single ended inverter whose input is coupled to a + input of the corresponding differential input; and, ii) a second single ended inverter whose input is coupled to a − input of the corresponding differential input. With respect to the differential output, the differential input further includes: i) a + output that is coupled to each said second single ended inverter output; ii) a − output that is coupled to each said first single ended inverter output.

Claims

1. An oscillator, comprising:

circuitry to affect the amount of supply current that flows through said oscillator'"'"'s delay stages in order to affect delay through said delay stage;

a delay stage comprising;

a) at least two differential inputs;

b) a pair of single ended inverters for each differential input, each pair of single ended inverters further comprising, for their corresponding differential input;

i) a first single ended inverter whose input is coupled to a + input of said corresponding differential input;

ii) a second single ended inverter whose input is coupled to a −

input of said corresponding differential input each said first single and second single ended inverter input being coupled to only one output node of another delay stage; and

,

c) a differential output, said differential output further comprising;

i) a + output that is coupled to each said second single ended inverter output;

ii) a −

output that is coupled to each said first single ended inverter output.

2. The oscillator of claim 1 wherein said delay stage further comprises another pair of single ended inverters between said + output and said −

output, a first inverter of said another pair of single ended inverters having an input coupled to said + output and an output coupled to said −

output, a second inverter of said another pair of single ended inverters having an input coupled to said −

output and an output coupled to said + output.

3. The oscillator of claim 2 wherein said oscillator delay stage is part of an oscillator having an odd number of delay stages.

4. The oscillator of claim 2 wherein said oscillator delay stage is part of an oscillator having an even number of delay stages.

5. The oscillator of claim 4 where:

$k_0><br><br>\frac{1}{N}<br><br>\underset{i=1}{\overset{i=\left(N-1\right)}{\sum <br><br>}}<br><br>\text{\hspace{1em}<br><br>}<br><br>{\left(-1\right)}^{\left(i+1\right)}<br><br>k_i<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{with}<br><br>\text{\hspace{1em}<br><br>}<br><br>k_1><br><br>0$

where;

a) k₀ is the drive strength of each inverter of said another pair of single ended inverters;

b) N is said even number of delay stages;

c) for each integer i from 1 to M, where M is the number of differential inputs of said oscillator delay stage;

k_i is the drive strength of each inverter of said pair of inverters coupled to the i^th differential input of said at least one differential input; and

,

d) for each integer i from M+1 to N−

1 (if any such integers);

k_i=0.

6. The oscillator of claim 5 wherein:

$k_0><br><br>\frac{1}{N}<br><br>\left(k_1-k_2\right)$

7. The oscillator of claim 5 wherein:

$k_0><br><br>\frac{1}{N}<br><br>\left(k_1-k_2+k_3\right)$

8. The oscillator of claim 1 wherein said oscillator that is designed as a series of N delay stages.

9. The oscillator of claim 8 wherein each delay stage within said oscillator has its differential output coupled to:

1) its next delay stage within said series; and

2) a delay stage that immediately follows within said series said next delay stage.

10. The oscillator of claim 9 wherein each delay stage within said oscillator has its differential output coupled to:

1) a primary differential input of its next delay stage within said series; and

2) a secondary differential input of a delay stage that immediately follows said next delay stage within said series.

11. The oscillator of claim 1 wherein said oscillator is a voltage controlled oscillator, said voltage controlled oscillator, said circuitry comprising:

a voltage-to-current converter, said voltage-to-current converter having an input coupled to an input of said voltage controlled oscillator;

12. The oscillator of claim 11 wherein said oscillator is part of a phase-lock-loop circuit.

13. The oscillator of claim 12 whether said oscillator delay stage further comprises another pair of single ended inverters between said + output and said −

output, a first inverter of said another pair of single ended inverters having an input coupled to said + output and an output coupled to said −

output, a second inverter of said another pair of single ended inverters having an input coupled to said −

output and an output coupled to said + output.

14. The oscillator of claim 13 wherein said oscillator has an odd number of delay stages.

15. The oscillator of claim 13 wherein said oscillator has an even number of delay stages.

16. The oscillator of claim 15 where:

$k_0><br><br>\frac{1}{N}<br><br>\underset{i=1}{\overset{i=\left(N-1\right)}{\sum <br><br>}}<br><br>\text{\hspace{1em}<br><br>}<br><br>{\left(-1\right)}^{\left(i+1\right)}<br><br>k_i<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{with}<br><br>\text{\hspace{1em}<br><br>}<br><br>k_1><br><br>0$

where;

a) k₀ is the drive strength of each inverter of said another pair of single ended inverters;

b) N is said even number of delay stages;

c) for each integer i from 1 to M, where M is the number of differential inputs of said oscillator delay stage;

k_i is the drive strength of each inverter of said pair of inverters coupled to the i^th differential input of said at least one differential input; and

,

d) for each integer i from M+1 to N−

1 (if any such integers);

k_i=0.

17. The oscillator of claim 16 wherein:

$k_0><br><br>\frac{1}{N}<br><br>\left(k_1-k_2\right)$

18. The oscillator of claim 16 wherein:

$k_0><br><br>\frac{1}{N}<br><br>\left(k_1-k_2+k_3\right)$

19. The oscillator of claim 12 wherein said oscillator is designed as a series of N delay stages.

20. The oscillator of claim 19 wherein each delay stage within said oscillator has its differential output coupled to;

1) its next delay stage within said series; and

2) a delay stage that immediately follows said next delay stage within said series.

21. The oscillator of claim 20 wherein each delay stage within said oscillator has its differential output coupled to:

1) a primary differential input of its next delay stage within said series; and

2) a secondary differential input of a delay stage that immediately follows said next delay stage within said series.

22. The machine readable medium having stored thereon a description of an oscillator, said oscillator comprising:

circuitry to affect the amount of supply current that flows through said oscillator'"'"'s delay stages in order to affect delay through said delay stages;

a delay stage comprising;

a) at least one differential input;

b) a pair of single ended inverters for each differential input, each pair of single ended inverters further comprising, for their corresponding differential input;

i) a first single ended inverter whose input is coupled to a + input of said corresponding differential input;

ii) a second single ended inverter whose input is coupled to a - input each said first and second single ended inverter input being coupled to only one output node of another delay stage

c) a differential output, said differential output further comprising;

i) a + output that is coupled to each said second single ended inverter output;

ii) a - output that is coupled to each said first single ended inverter output.

23. The machine readable medium of claim 22 where said oscillator delay stage further comprises another pair of single ended inverters between said - output and said - output, a first inverter of said another pair of single ended inverters having an input coupled to said + and an output coupled to said - , a second inverter of said another pair of single ended inverters having an input coupled to said - output and an output coupled to said + output

29. The machine readable medium of claim 22 wherein said oscillator has a series of N delay stages.

30. The machine readable medium of claim 29 wherein each delay stage within said oscillator has its differential output coupled to:

1) its next delay stage within said series; and

2) a delay stage that immediately follows said next delay stage within said series.

31. The machine readable medium of claim 30 wherein each delay stage within said oscillator has its differential output coupled to:

1) a primary differential input of its next delay stage within said series; and

2) a secondary differential input of a delay stage that immediately follows said next delay stage within said series.

32. The machine readable medium of claim 22 wherein said oscillator is a voltage controlled oscillator said circuit comprising:

a voltage-to-current converter, said voltage-to-current converter having an input coupled to an input of said voltage controlled oscillator

33. The machine readable medium of claim 32 wherein said voltage controller oscillator is part of a phase-lock-loop circuit.

34. The machine readable medium of claim 33 wherein said oscillator delay stage further comprises another pair of single ended inverters between said + output and said −

output, a first inverter of said another pair of single ended inverters having an input coupled to said + output and an output coupled to said −

output, a second inverter of said another pair of single ended inverters having an input coupled to said −

output and an output coupled to said + output.

35. The machine readable medium of claim 34 wherein said oscillator has an odd number of delay stages.

36. The machine readable medium of claim 34 wherein said oscillator has an even number of delay stages.

37. The machine readable medium of claim 36 where:

$k_0><br><br>\frac{1}{N}<br><br>\underset{i=1}{\overset{i=\left(N-1\right)}{\sum <br><br>}}<br><br>\text{\hspace{1em}<br><br>}<br><br>{\left(-1\right)}^{\left(i+1\right)}<br><br>k_i<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{with}<br><br>\text{\hspace{1em}<br><br>}<br><br>k_1><br><br>0$

where;

a) k₀ is the drive strength of each inverter of said another pair of single ended inverters;

b) N is said even number of delay stages; and

c) for each integer i from 1 to M, where M is the number of differential inputs of said oscillator delay stage;

k_i is the drive strength of each inverter of said pair of inverters coupled to the i^th differential input of said at least one differential input; and

,

d) for each integer i from M+1 N−

1 to N (if any such integers);

k_i=0.

38. The machine readable medium of claim 37 wherein:

$k_0><br><br>\frac{1}{N}<br><br>\left(k_1-k_2\right)$

39. The machine readable medium of claim 37 wherein:

$k_0><br><br>\frac{1}{N}<br><br>\left(k_1-k_2+k_3\right)$

40. The machine readable medium of claim 33 wherein said oscillator is described as a series of N delay stages.

41. The machine readable medium of claim 40 wherein each delay stage within said oscillator has its differential output coupled to:

1) its next delay stage within said series; and

2) a delay stage that immediately follows said next delay stage within said series.

42. The machine readable medium of claim 41 wherein each delay stage within said oscillator has its differential output coupled to:

1) a primary differential input of its next delay stage within said series; and

2) a secondary differential input of a delay stage that immediately follows said next delay stage within said series.

43. The machine readable medium of claim 23 wherein said description is in the format of a transistor level netlist.

44. The machine readable medium of claim 22 wherein said description describes said oscillator as a layout for said oscillator.

24. The machine readable medium of claim 24 wherein said oscillator has an odd number of delay stages.

25. The machine readable medium of claim 24 wherein said oscillator has an even number of delay stages.

26. The machine readable medium of claim 25 where:

$k_0><br><br>\frac{1}{N}<br><br>\underset{i=1}{\overset{i=\left(N-1\right)}{\sum <br><br>}}<br><br>\text{\hspace{1em}<br><br>}<br><br>{\left(-1\right)}^{\left(i+1\right)}<br><br>k_i<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{with}<br><br>\text{\hspace{1em}<br><br>}<br><br>k_1><br><br>0$

where;

a) k₀ is the drive strength of each inverter of said another pair of single ended inverters;

b) N is said even number of delay stages;

c) for each integer i from 1 to M, where M is the number of differential inputs of said oscillator delay stage;

k_i is the drive strength of each inverter of said pair of inverters coupled to the i^th differential input of said at least one differential input; and

,

d) for each integer i from M+1 to N−

1 (if any such integers);

k_i=0.

27. The machine readable medium of claim 26 wherein:

$k_0><br><br>\frac{1}{N}<br><br>\left(k_1-k_2\right)$

28. The machine readable medium of claim 26 wherein:

$k_0><br><br>\frac{1}{N}<br><br>\left(k_1-k_2+k_3\right)$