Method and system for improving memory interface data integrity in PLDs
First Claim
1. A method for optimizing data presentation to an external memory interface bus for a programmable logic device (PLD), comprising:
- determining whether to encode a data sequence to be sent to an external memory;
setting a status bit to indicate that the data sequence is encoded;
setting a parity bit based on a number of first logical value types in the data sequence and the status bit; and
sending the data sequence to the external memory.
3 Assignments
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Accused Products
Abstract
An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder is capable of setting a status bit to indicate that the data are encoded. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, along with the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data.
74 Citations
15 Claims
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1. A method for optimizing data presentation to an external memory interface bus for a programmable logic device (PLD), comprising:
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determining whether to encode a data sequence to be sent to an external memory; setting a status bit to indicate that the data sequence is encoded; setting a parity bit based on a number of first logical value types in the data sequence and the status bit; and sending the data sequence to the external memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for minimizing simultaneously switching output (SSO) effect on a memory interface bus, comprising:
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counting a number of logical high values in a data sequence; encoding bits in the data sequence if the number of logical high values in the data sequence is larger than one-half of a total number of bits in the data sequence; setting a status bit of the data sequence; and setting a parity bit of the data sequence, the parity bit being based on the number of logical high values in the data sequence and the status bit. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification