Method and system for improving memory interface data integrity in PLDs

• US 7,102,544 B1
• Filed: 05/31/2005
• Issued: 09/05/2006
• Est. Priority Date: 05/31/2005
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Liu, Hui
• Primary Examiner(s): Mai, Lam T.
• Application Number:
  US11/142,732
• Time in Patent Office: 462 Days
• Field of Search: 341 50- 70, 711/119, 711/117
• US Class Current: 341/51
• CPC Class Codes: G06F 11/1032 Simple parity

Abstract

An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder is capable of setting a status bit to indicate that the data are encoded. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, along with the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data.

Claims

1. A method for optimizing data presentation to an external memory interface bus for a programmable logic device (PLD), comprising:

determining whether to encode a data sequence to be sent to an external memory;

setting a status bit to indicate that the data sequence is encoded;

setting a parity bit based on a number of first logical value types in the data sequence and the status bit; and

sending the data sequence to the external memory.

2. The method of claim 1, wherein determining whether to encode the data sequence to be sent to the external memory includes,

determining whether a majority of bits in the data sequence is of the first logical value type.

3. The method of claim 2, wherein if the majority of bits are determined to be of the first logical value type, the method includes,

encoding the data sequence;

and

setting the status bit to the first logical value type.

4. The method of claim 2, wherein if the majority bits are determined to be of a second logical value type, the method includes,

maintaining the data sequence in an unencoded format;

and

setting the status bit to the second logical value type.

5. The method of claim 1, wherein the number of first logical value types in the data sequence and the status bit determines whether the parity bit is one of a logical high value type or a logical low value type.

6. The method of claim 1, further comprising:

retrieving the data sequence from the external memory;

separating the parity bit from the data sequence; and

checking the parity bit to detect an error in the data sequence.

7. The method of claim 6, wherein checking the parity bit to detect the error in the data sequence includes,

comparing the parity bit with the number of first logical value types in the data sequence to determine whether the parity bit correlates with the number of first logical value types.

8. The method of claim 6, further comprising:

decoding the data sequence.

9. A method for minimizing simultaneously switching output (SSO) effect on a memory interface bus, comprising:

counting a number of logical high values in a data sequence;

encoding bits in the data sequence if the number of logical high values in the data sequence is larger than one-half of a total number of bits in the data sequence;

setting a status bit of the data sequence; and

setting a parity bit of the data sequence, the parity bit being based on the number of logical high values in the data sequence and the status bit.

10. The method of claim 9, wherein the encoding bits in the data sequence includes, inverting the bits in the data sequence.

11. The method of claim 10, wherein, setting the status bit in the data sequence includes,

setting the status bit to a logical high value when the bits in the data sequence are encoded;

and

setting the status bit to a logical low value when the bits in the data sequence are not encoded.

12. The method of claim 9, wherein setting the parity bit includes,

setting the parity bit subsequent to setting the status bit.

13. The method of claim 9, wherein setting the parity bit includes,

setting the parity bit to a logical high value when the number of logical high values in the data sequence and the status bit is odd;

and

setting the parity bit to a logical low value when the number of logical high values in the data sequence and the status bit is even.

14. The method of claim 9, further comprising:

transmitting the data sequence over the memory interface bus;

identifying a next data sequence to be transmitted over the memory interface bus;

encoding bits in the next data sequence if the number of logical high values in the next data sequence is larger than half a number of bits in the next data sequence;

comparing states of corresponding bit positions of the next data sequence with the data sequence; and

simultaneously changing states for corresponding bit positions that are different between the next data sequence and the data sequence when going from the data sequence to the next data sequence on the external memory interface bus.

15. The method of claim 14, wherein a percentage of bits which are simultaneously changing states from logical high values to logical low values or from logical low values to logical high values is less than 50%.