Method and apparatus for obtaining power computation parameters

• US 7,102,556 B2
• Filed: 03/18/2005
• Issued: 09/05/2006
• Est. Priority Date: 08/19/2002
• Status: Expired due to Term

• Current Assignee: Silergy Semiconductor (Samoa) Ltd. (Silergy Corporation)
• Original Assignee: TDK Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: White, Bert
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US11/084,713
• Publication Number:
  US 20050225469A1
• Time in Patent Office: 536 Days
• Field of Search: 341/118, 341/120, 341/141, 341/143, 341/155
• US Class Current: 341/141
• CPC Class Codes: G01R 21/133 by using digital technique

Abstract

A method and apparatus for obtaining power computation parameters is presented. Accurate computation of power requires multiplying voltage and current at the same instant of time and integrating the results over time. The present invention provides a method of using a single Analog to Digital Converter to convert both voltage and current for all the phases of any electrical system and then digitally compensating for the phase error caused by the non-simultaneous sampling of the current and voltage signals. The compensating filter could be implemented as a simple interpolator, an all-pass filter, or a combination of both. A single multiplexer is used to select which signal is processed by the Analog to Digital Converter. By scheduling and converting the voltage and analog signals one at a time, potential for crosstalk is significantly reduced, power requirement is reduced, and die size requirement is reduced.

Claims

1. A method for obtaining power computation parameters comprising:

generating first digital signal from a plurality of analog signals, wherein said plurality of analog signals comprise a pair of current and voltage signals associated with each phase of a multi-phase system;

converting said first digital signal to a plurality of second digital signals, wherein each one of said plurality of second digital signals represents a digital form of one of said plurality of analog signals with a sample period of a first number of clock cycles, and wherein a digital current signal and a digital voltage signal associated with each phase are skewed in time by a sample interval difference of a second number of clock cycles; and

compensating one of said digital current signal and said digital voltage signal associated with each phase by a fractional sample period approximating said second number divided by said first number thereby providing digital equivalents of said plurality of analog signals at the same sample time for each phase.

2. The method of claim 1, wherein said generating said first digital signal comprises:

multiplexing said plurality of analog signals using a first clock signal to generate a single analog signal; and

converting said single analog signal to said first digital signal using a second clock signal.

3. The method of claim 2, wherein said converting said single analog signal comprises using oversampling techniques to convert said analog signal to said digital representation.

4. The method of claim 2, wherein said first clock signal is an integer multiple of said second clock signal.

5. The method of claim 1, wherein said compensating said plurality of second digital signals comprises passing an appropriate one of said plurality of second digital signals through an interpolation filter.

6. The method of claim 1, wherein said compensating said plurality of second digital signals comprises applying a high order interpolation circuit to appropriate ones of said plurality of second digital signals.

7. The method of claim 1, wherein said compensating said plurality of second digital signals comprises passing appropriate ones of said plurality of second digital signals through an allpass filter.

8. The method of claim 1, wherein said plurality of second digital signals comprises power computation parameters.

9. An apparatus for obtaining power computation parameters comprising:

a multiplexer using a clock signal to generate a single analog signal from a plurality of analog input signals, wherein said plurality of analog input signals comprise a plurality of pairs of current and voltage signals each corresponding to a respective phase of a multiphase analog power signal; and

an analog to digital converter receiving said single analog signal and providing a first digital signal;

a demultiplexer using said clock signal to generate a plurality of second digital signals from said first digital signal, wherein each one of said plurality of second digital signals represents a digital form of one of said plurality of analog signals having a waveform sample period; and

a processing unit comprising a phase correction module configured to compensate said second plurality of digital signals for timing skew associated with a digital current signal and a digital voltage signal corresponding to each phase, wherein said timing skew is approximated by dividing a time difference between a sample of said digital current signal and a sample of said digital voltage signal by a sample period of said digital current signal.

10. The apparatus of claim 9, wherein said phase correction module is an interpolation filter.

11. The apparatus of claim 9, wherein said phase correction module is a high order interpolation circuit.

12. The apparatus of claim 9, wherein said phase correction module is an allpass filter.

13. The apparatus of claim 9, wherein said processing unit is configured to provide DC offset compensation for each of said second plurality of digital signals.

14. The apparatus of claim 9, wherein said processing unit is configured to scale each of said second plurality of digital signals by a respective calibration factor.

15. The apparatus of claim 9, wherein said processing unit further comprises:

a summer;

a first multiplier configured to receive from said second plurality of digital signals a first digital voltage signal and a first digital current signal associated with a first phase of said multiphase power signal;

a first programmable coefficient circuit coupled to said first multiplier and providing a first power component to said summer;

a second multiplier configured to receive from said second plurality of digital signals a second digital voltage signal and a second digital current signal associated with a second phase of said multiphase power signal;

a second programmable coefficient circuit coupled to said second multiplier and providing a second power component to said summer;

a third multiplier configured to receive from said second plurality of digital signals a third digital voltage signal and a third digital current signal associated with a third phase of said multiphase power signal; and

a third programmable coefficient circuit coupled to said third multiplier and providing a third power component to said summer.

16. The apparatus of claim 15, wherein said processing unit further comprises:

a first selectable current interpolator receiving said second digital current signal;

a first adder configured to add an output of said first selectable current interpolator to said first digital current signal;

a second selectable current interpolator receiving said third digital current signal; and

a second adder configured to add an output of said second selectable current interpolator to said second digital current signal.

17. The apparatus of claim 15, wherein said processing unit further comprises:

a fourth multiplier configured to receive said first digital current signal and a ninety-degree offset version of said first digital voltage signal;

a fourth programmable coefficient circuit coupled to said fourth multiplier and providing a fourth power component to said summer;

a fifth multiplier configured to receive said second digital current signal and a ninety-degree offset version of said second digital voltage signal;

a fifth programmable coefficient circuit coupled to said fifth multiplier and providing a fifth power component to said summer;

a sixth multiplier configured to receive said third digital current signal and a ninety-degree offset version of said third digital voltage signal; and

a sixth programmable coefficient circuit coupled to said sixth multiplier and providing a sixth power component to said summer.