Five-level feed-back digital-to-analog converter for a switched capacitor sigma-delta analog-to-digital converter
First Claim
1. A reference voltage switching arrangement for a five level feed-back digital-to-analog converter used with a switched capacitor sigma-delta analog-to-digital converter, said reference voltage switching arrangement comprising:
- a plus reference voltage capacitor having a capacitance of C/2;
a minus reference voltage capacitor having a capacitance of C/2;
a first pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to plus and minus reference voltages, respectively;
a second pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to the minus and the plus reference voltages, respectively; and
a third switch adapted for switchably coupling the plus and minus reference voltage capacitors together, wherein the first pair of switches, the second pair of switches, and the third switch are sequenced in a charge phase and a transfer phase to produce five equally distributed charge levels of C*VREF, C*VREF/2, 0, −
C*VREF/2 and −
C*VREF, where VREF is a reference voltage.
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Abstract
A five-level feed-back digital-to-analog converter (DAC) in a switched capacitor sigma-delta analog-to-digital converter has an improved switching sequence that boosts from two to five the number of quantization levels of the feed-back DAC. Switching sequences are used to obtain five equally distributed charge levels C*V
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Citations
17 Claims
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1. A reference voltage switching arrangement for a five level feed-back digital-to-analog converter used with a switched capacitor sigma-delta analog-to-digital converter, said reference voltage switching arrangement comprising:
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a plus reference voltage capacitor having a capacitance of C/2; a minus reference voltage capacitor having a capacitance of C/2; a first pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to plus and minus reference voltages, respectively; a second pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to the minus and the plus reference voltages, respectively; and a third switch adapted for switchably coupling the plus and minus reference voltage capacitors together, wherein the first pair of switches, the second pair of switches, and the third switch are sequenced in a charge phase and a transfer phase to produce five equally distributed charge levels of C*V REF , C*VREF /2, 0, −
C*VREF /2 and −
C*VREF , where VREF is a reference voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A five level feed-back digital-to-analog converter for a switched capacitor sigma-delta analog-to-digital converter, said five level feed-back digital-to-analog converter comprising:
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a plus input voltage capacitor having a capacitance of A*C/2; a minus input voltage capacitor having a capacitance of A*C/2; a first pair of switches adapted for switchably coupling the plus and minus input voltage capacitors to plus and minus input voltages, respectively; a second pair of switches adapted for switchably coupling the plus and minus input voltage capacitors to the minus and the plus input voltages, respectively; a plus reference voltage capacitor having a capacitance of C/2; a minus reference voltage capacitor having a capacitance of C/2; a fifth pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to plus and minus reference voltages, respectively; a sixth pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to the minus and the plus reference voltages, respectively; and a seventh switch adapted for switchably coupling the plus and minus reference voltage capacitors together; a third plurality of switches coupled to the plus and minus input voltage capacitors and the plus and minus reference voltage capacitors, and adapted for switchably coupling a common mode voltage, V CM , to these capacitors; anda fourth pair of switches adapted for coupling the plus and minus input voltage capacitors and the plus and minus reference voltage capacitors to a differential input of an amplifier, wherein the switches are sequenced in a charge phase and a transfer phase to produce five equally distributed voltage outputs from the amplifier of A*V IN +VREF , A*VIN +VREF /2, A*VIN +0, A*VIN −
VREF /2 and A*VIN −
VREF , where A is gain, VIN is an input voltage, and VREF is a reference voltage. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method for producing five reference voltage levels in a feed-back digital-to-analog converter used with a switched capacitor sigma-delta analog-to-digital converter, said method comprising the steps of:
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providing a plus reference voltage capacitor having a capacitance of C/2; providing a minus reference voltage capacitor having a capacitance of C/2; producing a charge level of C*V REF bycoupling the plus and minus reference voltage capacitors to plus and minus reference voltages, respectively, during a charge phase, and coupling the plus and minus reference voltage capacitors to the minus and the plus reference voltages, respectively, during a transfer phase; producing a charge level of C*V REF /2 bycoupling the plus and minus reference voltage capacitors to the plus and minus reference voltages, respectively, during the charge phase, and coupling the plus and minus reference voltage capacitors together, during the transfer phase; producing a charge level of 0 by coupling the plus and minus reference voltage capacitors together during the charge phase and the transfer phase; producing a charge level of −
C*VREF /2 bycoupling the plus and minus reference voltage capacitors to the minus and the plus reference voltages, respectively, during the charge phase; and coupling the plus and minus reference voltage capacitors together, during the transfer phase; and producing a charge level of −
C*VREF bycoupling the plus and minus reference voltage capacitors to the minus and the plus reference voltages, respectively, during the charge phase; and coupling the plus and minus reference voltage capacitors to the plus and minus reference voltages, respectively, during the transfer phase. - View Dependent Claims (17)
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Specification