Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells

• US 7,102,924 B2
• Filed: 01/03/2005
• Issued: 09/05/2006
• Est. Priority Date: 01/18/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian, Mak, Alexander K., Pham, Long C.
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US11/028,906
• Publication Number:
  US 20050117401A1
• Time in Patent Office: 610 Days
• Field of Search: None
• US Class Current: 365/185.09
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

Techniques of overcoming a degradation of the apparent charge levels stored in one row of memory cells as a result of subsequently programming an adjacent row of memory cells. After storing the data of the subsequently programmed row elsewhere, the charge levels of its cells are driven to common level. The charge levels of the first row of cells then have a uniform influence from the charge levels of the second row, and, as a result, the chance of successfully reading the data stored in the first row is significantly increased.

Claims

1. A method of reading data stored as levels of charge in charge storage elements of memory cells of a first group, wherein the first group of charge storage elements are field coupled with charge storage elements of neighboring memory cells of at least a second group, comprising:

read the data stored in the storage elements of the first group of memory cells,

if valid data cannot be read from the first group of memory cells, then alter the levels of charge stored in the storage elements of the second group of memory cells, and

thereafter read the data stored in the storage elements of the first group of memory cells while the levels of charge stored in the memory cells of said at least the second group of memory cells remain altered.

2. The method of claim 1, additionally comprising:

thereafter restore the levels of charge stored in the storage elements of at least the second group of memory cells prior to being altered.

3. The method of claim 1, wherein it is determined whether valid data can be read from the first group of memory cells by use of an error correction code stored with the data in the first group of memory cells.

4. The method of claim 1, wherein the levels of charge stored in the storage elements of the second group of memory cells are altered to a common level of charge.

5. The method of claim 4, wherein the common level of charge is made to be substantially equal to a highest level of charge by which data are stored in the storage elements of the first group of memory cells.

6. The method of claim 1, wherein multiple levels of charge are stored in the individual charge elements of the first and second groups of memory cells in a manner to store more than one bit of data therein.

7. The method of claim 1, wherein the first and second groups of memory cells are part of a NAND array of memory cells.

8. The method of claim 1, wherein the memory cells of the first and second groups are flash EEPROM cells.

9. The method of claim 1, wherein the method is practiced in an array of memory cells wherein the first and second groups of memory cells include respective first and second adjacent rows of memory cells.

10. The method of claim 1, wherein the method is practiced in a memory system whose charge storage elements are formed of an electrically conductive material.

11. The method of claim 1, wherein the method is practiced in a memory system whose charge storage elements are formed of a dielectric material.