Read circuit of semiconductor and read method using a self-reference sensing technique

• US 7,102,945 B2
• Filed: 12/20/2004
• Issued: 09/05/2006
• Est. Priority Date: 10/29/2004
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tsuchida, Kenji, Miyamoto, Junichi, Iwata, Yoshihisa
• Primary Examiner(s): Lam, David
• Application Number:
  US11/014,862
• Publication Number:
  US 20060092734A1
• Time in Patent Office: 624 Days
• Field of Search: None
• US Class Current: 365/205
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A read circuit of a semiconductor memory according to the present invention is based on a self-reference sensing technique by which data stored in a memory cell is determined by first and second signals read out from a memory cell through first and second read operations. This read circuit includes a sense amplifier which determines the data stored in the memory cell based on a potential of an input node, a transfer transistor which is connected between the memory cell and the input node, a precharge circuit which sets the input node to a precharge potential, and a VBIAS generator which turns the transfer transistor cutoff based on the first signal.

Claims

1. A read circuit of a semiconductor memory, comprising:

a sense amplifier which determines data stored in a memory cell based on a potential of an input node;

a transfer transistor which is connected between the memory cell and the input node;

a precharge circuit which sets the input node to a precharge potential; and

a VBIAS generator which turns the transfer transistor cutoff based on a first signal obtained from the memory cell through a first read operation,

wherein the transfer transistor is turned on when a second signal obtained from the memory cell through a second read operation differs from the first signal.

2. The read circuit according to claim 1,

wherein the transfer transistor is an N-channel MOS transistor, and the precharge potential is a supply potential.

3. The read circuit according to claim 2,

wherein, when the first and second signals differ from each other, the potential of the input node drops from the supply potential.

4. The read circuit according to claim 3,

wherein the sense amplifier is configured by a series inverter circuit that includes a first inverter having a logical threshold value closer to the supply potential than to half of the supply potential, and a second inverter having a logical threshold value in the neighborhood of half of the supply potential.

5. The read circuit according to claim 1,

wherein the transfer transistor is a P-channel MOS transistor, and the precharge potential is a ground potential.

6. The read circuit according to claim 5,

wherein, when the first and second signals differ from each other, the potential of the input node rises from the ground potential.

7. The read circuit according to claim 6,

wherein the sense amplifier is configured by a series inverter circuit that includes a first inverter having a logical threshold value closer to the ground potential than to half of the supply potential, and a second inverter having a logical threshold value in the neighborhood of half of the supply potential.

8. The read circuit according to claim 1,

wherein the transfer transistor is a MOS transistor, and the VBIAS generator determines a gate potential based on the source potential of the MOS transistor and turns the transfer transistor cutoff.

9. The read circuit according to claim 8,

wherein, during the first read operation, the transfer transistor is cutoff, irrespective of a variation in the data or characteristics of the memory cells.

10. The read circuit according to claim 8,

wherein the source potential is generated according to the first signal.

11. The read circuit according to claim 8,

wherein the gate potential determined by the VBIAS generator is maintained from the first read operation until the second read operation.

12. The read circuit according to claim 1,

further comprising a constant current circuit which generates a read current for use in the first and second read operations.

13. The read circuit according to claim 12,

wherein the read current flows from the constant current circuit to the memory cell.

14. The read circuit according to claim 12,

wherein the read current flows from the memory cell to the constant current circuit.

15. The read circuit according to claim 1,

wherein a write operation is performed on the memory cell between the first read operation and the second read operation, and when the transfer transistor is turned on, the potential of the input node changes from the precharge potential.

16. A read method using a self-reference sensing technique, comprising:

setting an input node of a sense amplifier to a precharge potential;

turning a transfer transistor cutoff, based on a first signal obtained from a memory cell through a first read operation, the transfer transistor being connected between the memory and the input node; and

turning the transfer transistor on and changing the potential of the input node from the precharge potential, when a second signal obtained from the memory cell through a second read operation differs from the first signal.

17. The read method according to claim 16,

wherein the memory cell is a magnetoresistive device, and a magnetic field that is being applied to the magnetoresistive device is insufficient to cause magnetization inversion for the second read operation.

18. The read method according to claim 17,

wherein the magnetic field is a uniaxial magnetic field directed in a particular axial direction, when the magnetization inversion is caused by combining magnetic fields directed in two or more axial directions.

19. The read method according to claim 17,

wherein the magnetic field is generated from a write current that flows through one of write lines located in the vicinity of the memory cell.

20. The read method according to claim 17,

the magnetization inversion is performed by a toggle write technique.